Data processor capable of simultaneously executing two instructions

Claim 1

A data processor comprising: (1) an instruction fetch unit (640) for fetching therein from a memory (620) first and second instructions each having a predetermined bit length and for outputting therefrom the first and second instructions in parallel; (2) a first instruction decoder (644) for receiving as an input thereto an operation code of the first instruction supplied from said instruction fetch unit (640); (3) a second instruction decoder (645) for receiving as an input thereto an operation code of the second instruction supplied from said instruction fetch unit (640); (4) an instruction execution unit including at least a register file (650), an arithmetic and logic unit (651), and a shifter (652) for being controlled at least by either one of a decode result from said first instruction decoder (644) and a decode result from said second instruction decoder (645); and (5) a first comparator (132) for comparing information of a destination field (112) of the first instruction outputted from said instruction fetch unit (640), with information of a first source field (123) of the second instruction outputted from said instruction fetch unit (640); wherein said register file (650) includes a plurality of registers (R0, R1, R2, R3, ..., R31) and said data processor further includes a signal transmission path for supplying, under a control condition depending on an output from said first comparator (132), the output from the shifter (652) related to immediate data (114) of the first instruction to an input (656) of said arithmetic and logic unit (651) to bypass said register file (650).