Patent US2542374A successfully refreshed from Google Patents.
Patent EP0427119A2 successfully refreshed from Google Patents.
EP0427119A2
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EP
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Disk array controller with parity capabilities
Assignee: Compaq Computer Corp
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Filing: 1990-11-02
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Granted: —
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Expires: 2010-11-02
Abstract
Abstract A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface.
Inventors
- 👤 Ryan A. Callison
- 👤 Thomas W. Grieff
- 👤 Kenneth L. Bush
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 20:12
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1076; G06F11/1008; G06F3/0601; G06F3/0668; G06F3/0671; G06F3/0673
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
138 words
A disk data controller for transferring data with a disk array in a computer system, comprising: buffer memory for storing data to be transferred to or transferred from the disk array; a plurality of means for receiving data to be transferred to or transferred from the disk array; means coupled to the disk array and said plurality of data transfer means for selecting which of said plurality of data transfer means may transfer data with the disk array and for passing said data between said selected data transfer means and the disk array; and means coupled to said buffer memory and said plurality of data transfer means for selecting which of said plurality of data transfer means may transfer data with said buffer memory and for passing data between said selected data transfer means and said buffer memory.
Claim 2
Dependent Claim
138 words
A disk data controller for transferring data with a disk array in a computer system, comprising: buffer memory for storing data to be transferred to or transferred from the disk array; a plurality of means for receiving data to be transferred to or transferred from the disk array; means coupled to the disk array and said plurality of data transfer means for selecting which of said plurality of data transfer means may transfer data with the disk array and for passing said data between said selected data transfer means and the disk array; and means coupled to said buffer memory and said plurality of data transfer means for selecting which of said plurality of data transfer means may transfer data with said buffer memory and for passing data between said selected data transfer means and said buffer memory.
Claim 3
Dependent Claim
26 words
The controller of claim 1, further comprising: a microprocessor coupled to said plurality of data transfer means for providing transfer information to laid data transfer means.
Claim 4
Dependent Claim
38 words
The controller of claim 2, wherein said microprocessor is further coupled to said memory selection means and wherein said memory selection means includes said microprocessor in the selection of the means which transfer data with said buffer memory.
Claim 5
Dependent Claim
42 words
The controller of claim 2 or 3, wherein said microprocessor is further coupled to said disk array selection means and wherein said disk array selection means includes said microprocessor in the selection of the means which transfer data with the disk array.
Claim 6
Dependent Claim
25 words
The controller of any preceding claim, wherein each of said plurality of data transfer means includes means for providing an address to said buffer memory.
Claim 7
Dependent Claim
28 words
The controller of claim 5, wherein said address providing means increments the address each time said data transfer means is selected to transfer data with said buffer memory.
Claim 8
Dependent Claim
20 words
The controller of any of claims 2 to 6, wherein said microprocessor provides disk addressing information to the disk array.
Claim 9
Dependent Claim
23 words
The controller of any preceding claln, further comprising: means coupled to the computer system for transferring data to or from said buffer memory.
Claim 10
Dependent Claim
23 words
The controller of any preceding claln, further comprising: means coupled to the computer system for transferring data to or from said buffer memory.
Claim 11
Dependent Claim
28 words
The controller of claim 8, wherein said memory selection means includes said computer system means in the selection of the means which transfer data with said buffer memory.
Claim 12
Dependent Claim
21 words
The controller of any preceding claim, wherein one of said plurality of data transfer means includes means for developing parity data.
Claim 13
Dependent Claim
22 words
The controller of claim 10, wherein said parity data transfer means includes means for storing a plurality addresses of said buffer memory.
Claim 14
Dependent Claim
23 words
The controller of claim 11, wherein said parity data transfer means successively accesses said buffer memory from each of said plurality of addresses.
Claim 15
Dependent Claim
18 words
The controller of claim 12, wherein said parity data transfer means performs an XOR operation with each access.
Claim 16
Dependent Claim
33 words
The controller of claim 13, wherein said parity data transfer means includes means for providing the result of said XOR operation to said buffer memory at the last of said plurality of addresses.
Claim 17
Dependent Claim
26 words
The controller of claim 13 or 14, wherein said parity data transfer means includes means for indicating if the result of said XOR operation is zero.
References Cited (Backward Citations)
No citation records indexed.
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