Method and apparatus for independently resetting processors and cache controllers in multiple processor systems

Claim 2

A computer system of the type adapted to operate in response to coded program instructions stored in system memory devices, the system including a primary and one or more secondary processors interfaced to a common system bus for executing program instruction, and wherein the system is initialized in response to a system reset signal, a processor reset control system comprising: a. means responsive to the system reset signal for resetting the processors; b. means for generating a primary processor reset signal; c. means responsive to the primary processor reset signal for resetting only the primary processor.

Claim 3

the system of claim 1, wherein said means for generating a primary processor reset signal includes: instruction reset means responsive to address coded instructions present on the system bus to determine that a primary processor reset has been requested.

Claim 4

The system of claim 2, wherein said instruction reset means comprises: means for receiving address coded instructions and data via the system bus; decoding means for decoding said program instructions to determine that a primary processor reset has been requested; reset signal means responsive to said decoding means for generating a primary processor reset signal.

Claim 5

The system of claim 3, wherein said decoding means comprises: an address decoding circuit for address decoding of program instructions; a primary processor reset data register; means for generating a register select signal for enabling said primary processor reset register to receive data in response to program primary processor reset instructions; means for writing primary processor reset data to said processor reset data register.

Claim 6

The system of claim 4, wherein said reset signal means comprises: means responsive to the status of data in said primary processor reset register for generating a primary processor reset initiation signal; means responsive to the reset initiation signal for geneating a processor hold request signal; means for providing the processor hold request to the primary processor; means for delaying the generation of the primary processor reset signal until the primary processor is in a hold state; means for providing a reset signal to the processor.

Claim 7

The system of claim 5, further comprising: reset timing means for maintaining the primary processor reset signal active for a specified period.

Claim 8

The system of claim 6, wherein said reset timing means comprises: a counter circuit activated by the initiation of the primary processor reset signal; means, associated with said counter circuit, for deactivating the primary processor reset signal after the specified time period has elapsed.

Claim 9

The system of claim 1, further comprising: means for generating a secondary processor only reset signal; means responsive to the secondary processor reset signal for resetting only the secondary processor.

Claim 10

The system of claim 1, further comprising: means for generating a processor reset signal to reset all system processors in response to a system shutdown condition.

Claim 11

A computer system of the type adapted to operate in response to coded program instructions stored in system memory devices, the system including a processor for executing coded instructions, a system main memory for storing data and coded instructions, a cache memory for temporarily storing a duplication of a portion of the data and instructions stored in system memory for high speed access by the processor, and a cache memory controller interfacing with the processor, the cache memory and the main memory to determine whether instructions or data required by the processor are resident in cache memory, and wherein the cache controller and the processor interface via a system bus for transmitting data and system control signals, and where the system is initialized in response to a system reset signal, a processor reset control circuit comprising: a. means responsive to the system reset signal for resetting the processor and the cache controller; b. means responsive to program instructions for generating a processor reset signal; c. means responsive to the processor reset signal for resetting the processor only.

Claim 12

A computer system of the type adapted to operate in response to coded program instructions stored in system memory devices, the system including a processor for executing coded instructions, a system main memory for storing data and coded instructions, a cache memory for temporarily storing a duplication of a portion of the data and instructions stored in system memory for high speed access by the processor, and a cache memory controller interfacing with the processor, the cache memory and the main memory to determine whether instructions or data required by the processor are resident in cache memory, and wherein the cache controller and the processor interface via a system bus for transmitting data and system control signals, and where the system is initialized in response to a system reset signal, a processor reset control circuit comprising: a. means responsive to the system reset signal for resetting the processor and the cache controller; b. means responsive to program instructions for generating a processor reset signal; c. means responsive to the processor reset signal for resetting the processor only.

Claim 13

The system of claim 10, wherein said means for generating a processor reset signal includes: means responsive to address coded instructions present on the system but to determine that a processor reset has been requested.

Claim 14

The system of claim 11, wherein said instruction responsive reset means comprises: means for receiving address coded instructions and data via the system bus; decoding means for decoding program instructions to determine that a processor reset has been requested; reset signal means responsive to said decoding means for generating a processor reset signal.

Claim 15

The system of claim 12, wherein said decoding means comprieses; an address decoding circuit for decoding the address of program instruction; a processor reset data register; means responsive to said decoding circuit for enabling said processor reset register to receive data in response to processor reset instructions; means for writing processor reset data to said processor reset register.

Claim 16

The system of claim 13, wherein said reset signal means comprises: means responsive to the status of data in said processor reset register for generating a processor reset initiation signal; means responsive to the reset initialization signal for generating a processor hold request signal; means for providing the processor hold request signal to the processor; means for delaying the generation of a processor reset signal until the processor is in a hold state; means for providing a reset signal to the processor.