Patent EP0426283A2 successfully refreshed from Google Patents.
EP0426283A2
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EP
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Input row drivers for programmable logic devices
Assignee: STMicroelectronics lnc USA
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Filing: 1990-08-30
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Granted: —
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Expires: 2010-08-30
Abstract
Abstract Multi-function input pins in a programmable logic device are connected to select circuitry (82) which is programmed at device program time. Output signals generated by one or more output logic macrocells (48,50) are also connected to such select circuitry. The select circuitry generates a signal which is used to drive a row of the array. If an input pin used for providing a control signal, it is not connected to the array, and the output circuitry can drive that row of the array with an output signal which it generates, or with an input signal obtained from an associated input/output pin (60)(62).
Inventors
- 👤 Randy Charles Steele
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 16:25
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1731; H03K19/1732; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
91 words
An input circuit for a programmable logic device having an AND-OR array and a plurality of output circuit blocks, comprising: a row driver buffer having an output connected to the array; and a select circuit having an output connected to said row driver buffer, and having inputs connected to an input pin and to an output of at least one output circuit block; wherein one of the select circuit inputs is connected to the select circuit output according to program information stored with said select circuit when the device is programmed.
Claim 2
Dependent Claim
91 words
An input circuit for a programmable logic device having an AND-OR array and a plurality of output circuit blocks, comprising: a row driver buffer having an output connected to the array; and a select circuit having an output connected to said row driver buffer, and having inputs connected to an input pin and to an output of at least one output circuit block; wherein one of the select circuit inputs is connected to the select circuit output according to program information stored with said select circuit when the device is programmed.
Claim 3
Dependent Claim
22 words
The input circuit of Claim 1, wherein said select circuit has inputs connected to two output circuit blocks and the input pin.
Claim 4
Dependent Claim
35 words
The input circuit of Claim 1, wherein the input pin is also connected to an alternate buffer so that the input pin can be used to provide a control signal instead of an input signal.
Claim 5
Dependent Claim
60 words
The input circuit of Claim 1, wherein the output of the output logic block connected to said select circuit contains one of the following signals: a signal provided as input to a pin connected to the output logic block; a combinatorial logic signal generated by the output logic block; or a sequential logic signal generated by the output logic block.
Claim 6
Dependent Claim
42 words
The input circuit of Claim 4, wherein the output of the output logic block connected to said select circuit can instead contain the following signal: an output signal provided from a different output logic block not connected directly to said select circuitry.
Claim 7
Dependent Claim
75 words
A logic circuit for use in a programmable logic device having an AND-OR array, comprising: a row driver connected to the array; a selector connected to said row driver; a device input pin connected to said selector; and an output logic block having an input connected to the array, an input connected to a device input/output pin, an output connected to the device input/output pin, and an output connected to an input of said selector.
Claim 8
Dependent Claim
75 words
A logic circuit for use in a programmable logic device having an AND-OR array, comprising: a row driver connected to the array; a selector connected to said row driver; a device input pin connected to said selector; and an output logic block having an input connected to the array, an input connected to a device input/output pin, an output connected to the device input/output pin, and an output connected to an input of said selector.
Claim 9
Dependent Claim
47 words
The circuit of Claim 6, further comprising: a second output logic block having an input connected to the array, an input connected to a second device input/output pin, an output connected to the second device input/output pin, and an output connected to said an input of selector.
Claim 10
Dependent Claim
59 words
The circuit of Claim 6, wherein said output logic includes a second selector providing the output connected to an input of said selector, said second selector having inputs connected to: the device input/output pin; an output of a combinatorial logic circuit within said output logic circuit; and an output of a clocked logic device within said output logic circuit.
Claim 11
Dependent Claim
26 words
The circuit of Claim 8, wherein said second selector also has an input connected to a second device input/output pin through a second output logic block.
Claim 12
Dependent Claim
95 words
A programmable logic device, comprising: an AND-OR array; a plurality of dedicated device input pins connected to said array through row buffers; a plurality of output logic blocks having inputs connected to said array, and having inputs and outputs connected to device input/output pins corresponding therewith; an input selector having an output connected to a row driver connected to said array, and having at least one input connected to an output logic block; and an input pin connected to an input of said input selector and to an alternative input buffer for performing control functions.
Claim 13
Dependent Claim
95 words
A programmable logic device, comprising: an AND-OR array; a plurality of dedicated device input pins connected to said array through row buffers; a plurality of output logic blocks having inputs connected to said array, and having inputs and outputs connected to device input/output pins corresponding therewith; an input selector having an output connected to a row driver connected to said array, and having at least one input connected to an output logic block; and an input pin connected to an input of said input selector and to an alternative input buffer for performing control functions.
Claim 14
Dependent Claim
24 words
The device of Claim 10, wherein each of said output logic blocks further includes an output to a row driver connected to said array.
Claim 15
Dependent Claim
61 words
The device of Claim 10, wherein at least one output logic block further includes: selection means for providing to said input selector a signal selected from the following: an output of a combinatorial logic circuit within the output logic block, an output from a clocked device within the output logic block, and a signal present on the corresponding device input/output pin.
Claim 16
Dependent Claim
12 words
The device of Claim 12, wherein said selection means comprises a multiplexer.
Claim 17
Dependent Claim
38 words
The device of Claim 12, wherein said selection means provides the signal with the further possible selection of: a signal present on a device input/output pin corresponding to output logic block not connected directly to said input selector.
References Cited (Backward Citations)
No citation records indexed.
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