EP0426174A2 — Semiconductor integrated circuit

Claim 1

Independent Claim 151 words

A semiconductor integrated circuit comprising an inverter having a drive MIS transistor (Q1, Q2) a load device (R1, R2) and a transfer MIS transistor (Q3, Q4) for transferring the output of the inverter (Q1, R1; Q2, R2) to a data line (BL, BL ), the channel of the drive MIS transistor being formed in the surface portion of a semiconductor substrate (100; 300), and the load device being formed of a first silicon layer (108-112; 308-312) provided through an insulating layer on said semiconductor substrate, characterized in that the channel of the transfer MIS transistor being formed of a part of a second silicon layer (114-119; 313-318) provided through an insulating layer (152; 352) on said first silicon layer, wherein one of two regions of said second silicon layer is electrically connected to the output of said inverter while the other region is connected to said data line (BL, BL ).

Claim 2

Dependent Claim 151 words

A semiconductor integrated circuit comprising an inverter having a drive MIS transistor (Q1, Q2) a load device (R1, R2) and a transfer MIS transistor (Q3, Q4) for transferring the output of the inverter (Q1, R1; Q2, R2) to a data line (BL, BL ), the channel of the drive MIS transistor being formed in the surface portion of a semiconductor substrate (100; 300), and the load device being formed of a first silicon layer (108-112; 308-312) provided through an insulating layer on said semiconductor substrate, characterized in that the channel of the transfer MIS transistor being formed of a part of a second silicon layer (114-119; 313-318) provided through an insulating layer (152; 352) on said first silicon layer, wherein one of two regions of said second silicon layer is electrically connected to the output of said inverter while the other region is connected to said data line (BL, BL ).

Claim 3

Dependent Claim 40 words

The semiconductor integrated circuit according to claim 1, characterized by a first interconnect layer (113) which forms the gate electrode of the transfer MIS transistor and is located between insulating layers (152, 153) between said first and second silicon layers.

Claim 4

Dependent Claim 45 words

The semiconductor integrated circuit according to claim 2, characterized in that the insulating layer (152) between the first interconnect layer (113) and the first silicon layer (108-112) is thicker than the insulating layer (153) between the first interconnect layer and the second silicon layer (114-119).

Claim 5

Dependent Claim 39 words

The semiconductor integrated circuit according to claim 2 or 3, characterized in that the insulating layer (152) between said first interconnect layer (113) and the first silicon layer is made of silicon oxide which is almost free of impurities.

Claim 6

Dependent Claim 41 words

The semiconductor integrated circuit according to claim 1, characterized by a first interconnect layer (319) which forms the gate electrode of the transfer MIS transistor (Q3, Q4) and is located on said second silicon layer (313-318) through an insulating layer (353).

Claim 7

Dependent Claim 45 words

The semiconductor integrated circuit according to claim 5, characterized in that said insulating layer (352) between the first silicon layer (308-312) and the second silicon layer (313-318) is thicker than the insulating layer (353) between said first interconnect layer (319) and the second silicon layer.

Claim 8

Dependent Claim 44 words

The semiconductor integrated circuit according to any of the preceding claims, characterized in that said first layer of silicon (108-112; 308-312) is formed through an insulating layer (151; 351) on the gate electrode (106, 107; 306, 307) of said drive MIS transistor (Q1, Q2).

Claim 9

Dependent Claim 50 words

The semiconductor integrated circuit according to claim 7, characterized in that said load device is composed of a load MIS transistor, having as its channel a local region (109, 110; 309, 310) of said first layer of silicon which is located on the gate electrode of the drive MIS transistor.

Claim 10

Dependent Claim 29 words

The semiconductor integrated circuit according to claim 8, characterized in that the load MIS transistor and the drive MIS transistor share the same gate electrode (106, 107; 306, 307).

Claim 11

Dependent Claim 58 words

The semiconductor integrated circuit according to claim 9, characterized in that the insulating layer (151; 351) between the gate electrode (106, 107; 306, 307) of said drive MIS transistor (Q1, Q2) and said load MIS transistor (R1, R2) is thinner than the insulating layer (152; 352) between the first layer of silicon and the second layer of silicon.

Claim 12

Dependent Claim 90 words

The semiconductor integrated circuit according to claim 9, characterized by a third silicon layer (113) forming the gate electrode of the transfer MIS transistor (Q3, Q4) and being located between said first and second layers of silicon, an insulating layer (152) between the first and third layers of silicon being thicker than the insulating layer (151) between the first layer of silicon and the gate electrode (106, 107) of said drive and load MIS transistors and thicker than the insulating layer (153) between the second and third layers of silicon.

Claim 13

Dependent Claim 42 words

The semiconductor integrated circuit according to and of the preceding claims, characterized in that the insulating layer (152, 153; 352) between the first and second layers of silicon (108-112, 114-119; 308-312, 313-318) is formed of silicon oxide that contains almost no impurities.

Claim 14

Dependent Claim 33 words

The semiconductor integrated circuit according to claim 11, characterized in that the insulating layer (152) between the first and third layers of silicon is formed of silicon oxide that contains almost no impurities.

Claim 15

Dependent Claim 105 words

The semiconductor integrated circuit according to claim 8, characterized in that a local region (108; 308) of the first silicon layer, which forms the drain of the load MIS transistor (R1, R2), is electrically connected to a drain diffusion region (101, 102; 301, 302) of the drive MIS transistor (Q1, Q2) through a first contact hole (134, 135; 334, 335), and that a local region (114, 115, 313, 314) of the second layer of silicon forming the drain or source of the transfer MIS transistor (Q3, Q4) is electrically connected to the first layer of silicon through a second contact hole (136, 137; 336, 337).

Claim 16

Dependent Claim 53 words

The semiconductor integrated circuit according to any of the preceding claims, characterized in that said data line (BL, BL ) is in contact with the second layer of silicon, and a third contact hole (138, 139; 338, 339) being formed above a part of a source diffusion region of the drive MIS transistor.

Claim 17

Dependent Claim 34 words

The semiconductor integrated circuit according to claim 15, characterized in that said third contact hole (138, 139; 338, 339) is formed above a part of the first layer of silicon (118, 119; 317, 318).

Claim 18

Dependent Claim 31 words

The semiconductor integrated circuit according to any of claims 8 to 16, characterized in that the drive MIS transistor is of N type and the load MIS transistor of P type.

Claim 19

Dependent Claim 42 words

The semiconductor integrated circuit according to any of the preceding claims, characterized by a second inverter formed in the same way as said first inverter in a region adjacent to the first inverter, a bi-stable circuit being composed of the two inverters.

Claim 20

Dependent Claim 21 words

The semiconductor integrated circuit according to claim 18, characterized in that the bi-stable circuit forms a memory cell of an SRAM.

Claim 21

Dependent Claim 61 words

A semiconductor integrated circuit comprising a memory cell having drive MIS transistors (Q1, Q2) whose channels are formed in a surface portion of a monocrystalline silicon substrate, load MIS transistors (R1, R2) and transfer HIS transistors (Q3, Q4) whose channels are formed in a monocrystalline silicon thin film or a polycrystalline silicon thin film provided on top of an insulating layer.

Claim 22

Dependent Claim 61 words

A semiconductor integrated circuit comprising a memory cell having drive MIS transistors (Q1, Q2) whose channels are formed in a surface portion of a monocrystalline silicon substrate, load MIS transistors (R1, R2) and transfer HIS transistors (Q3, Q4) whose channels are formed in a monocrystalline silicon thin film or a polycrystalline silicon thin film provided on top of an insulating layer.

Claim 23

Dependent Claim 70 words

The semiconductor integrated circuit according to claim 20, characterized in that the transfer MIS transistors (Q3, Q4) are formed on top of the load HIS transistors (R1, R2) through an insulating layer and that at least a portion of a contact between the transfer MIS transistors (Q3, Q4) and a bit line pair (BL, BL ) is formed on a VDD power source interconnection or a VSS power source interconnection.

Claim 24

Dependent Claim 188 words

A semiconductor integrated circuit comprising a static memory cell being composed of drive HIS transistors (Q1, Q2), whose channels are formed in the surface portion of a semiconductor substrate, and load HIS transistors (R1, R2) and transfer MIS transistors (Q3, Q4) whose channels are formed in a semiconductor thin film layer provided on an insulating layer, characterized in that the transfer MIS transistors (Q3, Q4) are formed on top of the load HIS transistors (R1, R2) through a first insulating layer, at least a portion of said first insulating layer that contacts the channels of the load HIS transistors (R1, R2) or the channels of the transfer HIS transistor (Q3, Q4) being thicker than a gate insulating layer of the load HIS transistors and the transfer HIS transistors, and that an interconnection of a bit line pair (BL BL ) is formed on the transfer HIS transistors (Q3, Q4) through a second insulating layer, at least that part of the second insulating layer that contacts the channels of the HIS transistors (Q3, Q4) being made thicker than the gate insulating layer of the transfer MIS transistors (Q3, Q4).

Claim 25

Dependent Claim 188 words

A semiconductor integrated circuit comprising a static memory cell being composed of drive HIS transistors (Q1, Q2), whose channels are formed in the surface portion of a semiconductor substrate, and load HIS transistors (R1, R2) and transfer MIS transistors (Q3, Q4) whose channels are formed in a semiconductor thin film layer provided on an insulating layer, characterized in that the transfer MIS transistors (Q3, Q4) are formed on top of the load HIS transistors (R1, R2) through a first insulating layer, at least a portion of said first insulating layer that contacts the channels of the load HIS transistors (R1, R2) or the channels of the transfer HIS transistor (Q3, Q4) being thicker than a gate insulating layer of the load HIS transistors and the transfer HIS transistors, and that an interconnection of a bit line pair (BL BL ) is formed on the transfer HIS transistors (Q3, Q4) through a second insulating layer, at least that part of the second insulating layer that contacts the channels of the HIS transistors (Q3, Q4) being made thicker than the gate insulating layer of the transfer MIS transistors (Q3, Q4).

Claim 26

Dependent Claim 30 words

The semiconductor integrated circuit according to claim 22, characterized in that the semiconductor substrate is a monocrystalline silicon substrate and the semiconductor thin film is a polycrystalline silicon thin film.

Claim 27

Dependent Claim 52 words

The semiconductor integrated circuit according to claim 22, characterized in that said first and second insulating layers which contact at least a portion of the channels of either the load HIS transistors (R1, R2) or the transfer MIS transistors (Q3, Q4) are formed of silicon oxide that is almost free of impurities.

Claim 28

Dependent Claim 94 words

A semiconductor integrated circuit comprising a static memory cell composed of drive MIS transistors (Q1, Q2), whose channels are formed in the surface portion of a semiconductor substrate, and load HIS transistors (R1, R2) and transfer HIS transistors (Q3, Q4), characterized in that the channels of the load MIS transistors and transrer HIS transistors are formed in a layer of semiconductor thin film provided on an insulating layer, and that the gate electrode of the transfer HIS transistors (Q3, Q4) are formed on top of the semiconductor thin film through a gate insulating layer.

Claim 29

Dependent Claim 94 words

A semiconductor integrated circuit comprising a static memory cell composed of drive MIS transistors (Q1, Q2), whose channels are formed in the surface portion of a semiconductor substrate, and load HIS transistors (R1, R2) and transfer HIS transistors (Q3, Q4), characterized in that the channels of the load MIS transistors and transrer HIS transistors are formed in a layer of semiconductor thin film provided on an insulating layer, and that the gate electrode of the transfer HIS transistors (Q3, Q4) are formed on top of the semiconductor thin film through a gate insulating layer.

Claim 30

Dependent Claim 53 words

The semiconductor integrated circuit according to any of claims 20 to 25, characterized in that the drive HIS transistors (Q1, Q2) and the transfer HIS transistors (Q3, Q4) are of a first conductivity type and the load HIS transistors (R1, R2) are of a second conductivity type different from the first conductivity type.

Claim 31

Dependent Claim 53 words

The semiconductor integrated circuit according to any of claims 20 to 25, characterized in that the drive MIS transistors (Q1, Q2) are of a first conductivity type and the transfer MIS transistors (Q3, Q4) and the load HIS transistors (R1, R2) are of a second conductivity type different from the first conductivity type.

Claim 32

Dependent Claim 28 words

The semiconductor integrated circuit according to any of claims 26 and 27, characterized in that said first conductivity type is N and said second conductivity type is p.

Claim 33

Dependent Claim 34 words

The semiconductor integrated circuit according to claim 25, characterized in that the semiconductor substrate (300) is a monocrystalline silicon substrate and the layer of semiconductor thin film is a polycrystalline silicon thin film layer.

Claim 34

Dependent Claim 34 words

The semiconductor integrated circuit according to claim 25, characterized in that the semiconductor substrate (300) is a monocrystalline silicon substrate and the layer of semiconductor thin film is a monocrystalline silicon thin film layer.

Claim 35

Dependent Claim 50 words

The semiconductor integrated circuit according to claim 25, characterized by an interlayer insulating layer that contacts a least a portion of the channels of either the load HIS transistors (R1, R2) or the transfer HIS transistors (Q3, Q4) and is formed of silicon oxide that is almost free of impurities.

Claim 36

Dependent Claim 36 words

The semiconductor integrated circuit according to claim 31, characterized in that said interlayer insulating layer is thicker than a gate insulating layer of the load MIS transistors (R1, R2) or the transfer HIS transistors (Q3, Q4).

Semiconductor integrated circuit

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