Patent EP0425302A2 successfully refreshed from Google Patents.
EP0425302A2
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Digital phase lock loop decoder
Assignee: NCR International Inc
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Filing: 1990-10-26
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Granted: —
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Expires: 2010-10-26
Abstract
Abstract A digital phase lock loop decoder for decoding Manchester encoded data includes a controllable delay line (52) which provides a PLL CLOCK signal, which is delayed in respective further delay lines (58,62) and a compensating delay (66), to provide three phased clock signals (CLK1,CLK2,CLK3) defining a window for sampling the incoming data signal (RD). The sampled signals are applied to phase compare logic (86) which provides control signals for a counter (96), in dependence on the samples in the current and previous windows. The 7-bit counter output is fed back to control the phase of the controllable delay line (52) such that the central phased clock signal (CLK2) coincides with the mid-bit data transition. When data is not being received a delay correction section (34) continuously updates a compensating value which compensates for delay variations and is stored in a latch (142) for use during data reception.
Inventors
- 👤 Hans Van Driest
- 👤 Hendrik Van Bokhorst
- 👤 Richard Kruithof
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 17:33
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331; H03; H03M; H03M5/00; H03M5/02; H03M5/04; H03M5/06; H03M5/12; H04L7/04; H04L7/041; H04L7/046
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
252 words
A digital phase lock loop decoder for decoding input data signals (RD) occurring at a predetermined nominal rate, characterized by clock signal supply means (44) adapted to supply a first clock signal at said predetermined nominal rate, first delay line means (52) adapted to delay said clock signal by a controllable delay time to provide a second clock signal (PLL CLOCK), second delay line means (58,62,66) adapted to receive said second clock signal (PLL CLOCK) and to provide a plurality of delayed clock signals (CLK1, CLK2, CLK3) having respective phased delay times relative to said second clock signal (PLL CLOCK), sampling means (70,74,78) responsive to said delayed clock signals (CLK1,CLK2,CLK3) and to said input data signals (RD) and adapted to provide a plurality of signal samples; (Q1,Q2,Q3) of said input data signals, phase compare logic means (86) responsive to said second clock signal (PLL CLOCK) and to said plurality of signal samples (Q1,Q2,Q3) and adapted to provide counter control signals (FINE,INH,U/D) adapted to control the operation of counter means (96), feedback means (103,104) coupled between an output of said counter means (96) and said first delay line means (52) and adapted to control said controllable delay time, thereby controlling the phase of said second clock signal (PLL CLOCK) to correspond with the phase of a selected one (CLK2) of said plurality of delayed clock signals (CLK1,CLK2,CLK3), and data output means (20,80) coupled to said sampling means (70,74,78) and adapted to provide decoded output data signals corresponding to said input data signals (RD).
Claim 2
Dependent Claim
252 words
A digital phase lock loop decoder for decoding input data signals (RD) occurring at a predetermined nominal rate, characterized by clock signal supply means (44) adapted to supply a first clock signal at said predetermined nominal rate, first delay line means (52) adapted to delay said clock signal by a controllable delay time to provide a second clock signal (PLL CLOCK), second delay line means (58,62,66) adapted to receive said second clock signal (PLL CLOCK) and to provide a plurality of delayed clock signals (CLK1, CLK2, CLK3) having respective phased delay times relative to said second clock signal (PLL CLOCK), sampling means (70,74,78) responsive to said delayed clock signals (CLK1,CLK2,CLK3) and to said input data signals (RD) and adapted to provide a plurality of signal samples; (Q1,Q2,Q3) of said input data signals, phase compare logic means (86) responsive to said second clock signal (PLL CLOCK) and to said plurality of signal samples (Q1,Q2,Q3) and adapted to provide counter control signals (FINE,INH,U/D) adapted to control the operation of counter means (96), feedback means (103,104) coupled between an output of said counter means (96) and said first delay line means (52) and adapted to control said controllable delay time, thereby controlling the phase of said second clock signal (PLL CLOCK) to correspond with the phase of a selected one (CLK2) of said plurality of delayed clock signals (CLK1,CLK2,CLK3), and data output means (20,80) coupled to said sampling means (70,74,78) and adapted to provide decoded output data signals corresponding to said input data signals (RD).
Claim 3
Dependent Claim
37 words
A digital phase lock loop decoder according to claim 1, characterized by delay correction means (34) coupled to said first and second delay line means (52;58,62,66) and adapted to compensate for variations in the delay times thereof.
Claim 4
Dependent Claim
77 words
A digital phase lock loop decoder according to claim 2, characterized in that said first delay line means (52) includes a first delay line (170) having a plurality of individual delay cells (172), by delay measuring means (120,124,130,134) adapted to provide a measured value (LENGTH) representing the number of said delay cells (172) having a delay equal to the period of said first clock signal, and by storage means (142) adapted to store said measured value (LENGTH).
Claim 5
Dependent Claim
44 words
A digital phase lock loop decoder according to claim 3, characterized in that said second delay line means (58,62,66) includes second and third delay lines coupled to said storage means (142) and having controllable delay times determined in dependence on said measured value (LENGTH).
Claim 6
Dependent Claim
39 words
A digital phase lock loop circuit according to any one of claims 2 to 4, characterized in that said delay correction means (34) is adapted to be operative only when said input data signals (RD) are not being received.
Claim 7
Dependent Claim
74 words
A digital phase lock loop decoder according to any one of the preceding claims, characterized in that said phase compare logic means (86) includes a storage element (200) adapted to store an immediately preceding plurality of said signal samples (Q10,Q20,Q30), and logic circuit means (224) adapted to provide said counter control signals (FINE,INH,U/D) in dependence on the current plurality of said signal samples (Q1,Q2,Q3) and said immediately preceding plurality of said signal samples (Q10,Q20,Q30).
Claim 8
Dependent Claim
23 words
A digital phase lock loop decoder according to claim 6, characterized in that said counter means (96) includes a cyclic up/down counter (180,186,192,200).
Claim 9
Dependent Claim
41 words
A digital phase lock loop decoder according to claims 3 and 7, characterized in that said storage means (142) is coupled to said cyclic up/down counter (180,186,192,200), whereby said cyclic up/down counter (180,186,192,200) cycles between zero and said measured value (LENGTH).
Claim 10
Dependent Claim
68 words
A digital phase lock loop decoder according to claim 7 or claim 8, characterized in that said cyclic up/down counter (180,186,192,200) includes increment generating means (180) having inputs coupled to outputs of said phase compare logic means (86) and adapted to generate a step size for incrementing or decrementing said counter, the value of said selectable step size being dependent on one of said counter control signals (FINE).
Claim 11
Dependent Claim
38 words
A digital phase loop decoder according to claim 8 and claim 9, characterized in that said storage means (142) is coupled to said increment generator (180), whereby said step size is further dependent on said measured value (LENGTH).
Claim 12
Dependent Claim
55 words
A digital phase lock loop decoder according to any one of the preceding claims, characterized by preamble timer means (36) adapted to provide a time-out signal (INTEGR) after the lapse of a time corresponding to a preamble portion of said received data signals (RD), said time-out signal (INTEGR) being applied to said counter means (96).
Claim 13
Dependent Claim
27 words
A digital phase lock loop decoder according to any one of the preceding claims, characterized in that said input data signals (RD) are in Manchester coded form.
References Cited (Backward Citations)
No citation records indexed.
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