Patent EP0424964A2 successfully refreshed from Google Patents.
EP0424964A2
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EP
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Read only memory device
Assignee: Sony Corp
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Filing: 1990-10-26
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Granted: —
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Expires: 2010-10-26
Abstract
Abstract read-only memory device includes a number of MIS transistors forming memory cells arranged in a matrix configuration (1) to provide a NOR type memory device with high current driving capability for the memory cells. Bit lines (B i to B 3 ) and column lines (C 1 ,C 2 ) are arrayed alternately in common in each cell column so as to be used in common by adjacent memory cells in the word line extending direction. The bit lines for reading out signals from the memory cells function as the sources or drains of the MIS transistors of the memory cells, whereas the column lines for supplying the constant voltage to the memory cells function as the drains or sources of the MIS transistors of the memory cells. For column selection, there is provided a first selection switch (2) for selecting a group consisting of a plurality of bit lines and a plurality of column lines. A second selection switch and (Ti to T 4 ) a third selection switch (T s to Tg) are provided for selecting the bit line and the column line of the group, respectively. Since the bit lines and the column lines may be used fixedly, the second and the third selection switches may be arranged with a layout allowance and, if these second and third selection switches are formed by MIS transistors similar to those of the memory cells, the direction in common with the memory cells may be the channel direction to contribute to improved circuit integration. The MIS transistor constituting the memory cell may be of such a construction in which the source and drain regions may be provided below the thick insulating film formed on the substrate surface, such as field oxide film. This results in more effective utilization of the area on the substrate to realize a higher degree of integration. The self-alignment process promotes the circuit integration more effectively.
Inventors
- 👤 Akira C/O Sony Corporation Nakagawara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:51
CPC Classifications
H; H10; H10B; H10B20/00; G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C17/126; Y; Y10; Y10S; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
281 words
1) A read-only memory device for storing programmed data and subsequently reading out the stored data whenever the necessity arises, comprising a plurality of memory cells arranged in a matrix configuration (1) and including MIS transistors which may be selectively set to a high threshold voltage or to a low threshold voltage in accordance with programmed data, a plurality of word lines (Wi to W 4 ) used in common in each row of said cells and functioning as gates of said MIS transistors, a plurality of bit lines (B i to B 2 ) arranged substantially orthogonally to said word lines, said bit lines functioning as one of the sources or the drains of said MIS transistors and being used in common for data read-out by one of adjacent columns of said memory cells, a plurality of column lines (C1,C 2 ) arranged between said bit lines in alternation with and parallel to said bit lines, said column lines being used in common by the other of adjacent columns of said memory cells and functioning as the other of said sources or drains of said MIS transistors of columns of said cells, a potential difference higher than said low threshold voltage and lower than said high threshold voltage of said MIS transistor being applied on selection with respect to the voltage at said word line first selection means (2) for selecting groups each consisting of a plurality of said bit lines and a plurality of said column lines, second selection means (T i to T 4 ) for selecting said bit lines in each group, and third selection means (Ts to Ts) for selecting said column lines in each group.
Claim 2
Dependent Claim
281 words
1) A read-only memory device for storing programmed data and subsequently reading out the stored data whenever the necessity arises, comprising a plurality of memory cells arranged in a matrix configuration (1) and including MIS transistors which may be selectively set to a high threshold voltage or to a low threshold voltage in accordance with programmed data, a plurality of word lines (Wi to W 4 ) used in common in each row of said cells and functioning as gates of said MIS transistors, a plurality of bit lines (B i to B 2 ) arranged substantially orthogonally to said word lines, said bit lines functioning as one of the sources or the drains of said MIS transistors and being used in common for data read-out by one of adjacent columns of said memory cells, a plurality of column lines (C1,C 2 ) arranged between said bit lines in alternation with and parallel to said bit lines, said column lines being used in common by the other of adjacent columns of said memory cells and functioning as the other of said sources or drains of said MIS transistors of columns of said cells, a potential difference higher than said low threshold voltage and lower than said high threshold voltage of said MIS transistor being applied on selection with respect to the voltage at said word line first selection means (2) for selecting groups each consisting of a plurality of said bit lines and a plurality of said column lines, second selection means (T i to T 4 ) for selecting said bit lines in each group, and third selection means (Ts to Ts) for selecting said column lines in each group.
Claim 3
Dependent Claim
19 words
2) The read-only memory device according to claim 1, wherein said second and third selection means comprise MIS transistors.
Claim 4
Dependent Claim
55 words
3) The read-only memory device according to claim 2, wherein said bit lines and said column lines are formed in a striped pattern on a substrate and wherein a direction substantially orthogonal to the longitudinal direction of said striped pattern is the channel direction of said MIS transistors constituting said second and third selection means.
Claim 5
Dependent Claim
34 words
4) The read-only memory device according to claim 1 or 3, wherein said second selection means is arranged in opposition to said third selection means with an array of said memory cells in- between.
Claim 6
Dependent Claim
38 words
5) The read-only memory device according to claim 1, wherein said memory cells in the matrix configuration are divided into blocks along the bit lines and wherein said first selection means are used in common in each block.
Claim 7
Dependent Claim
25 words
6) The read-only memory device according to claim 1, wherein load circuits are arranged at terminal ends of each bit line and each column line.
Claim 8
Dependent Claim
37 words
7) The read-only memory device according to claim 6, wherein said memory cells in the matrix configuration are divided into blocks along the bit lines and wherein the load circuits are used in common by each block.
Claim 9
Dependent Claim
141 words
8) A read-only memory device comprising a semiconductor substrate of a first conductivity type a plurality of first insulating films of increased film thicknesses formed in parallel stripes on the surface of said semiconductor substrate of the first conductivity type. an impurity region of a second conductivity type formed on said semiconductor substrate below said first insulating films, a plurality of second nsulating films of a film thickness lesser than that of said first insulating films, said second insulating films having formed between said first insulating films on the surface of said semiconductor substrate, and a plurality of electrode layers formed in a pattern of stripes extending parallel to one another in a direction substantially orthogonai to said first insulating films on said first insulating films, programming being made by selectively introducing impurities into the substrate surface below said electrode layers.
Claim 10
Dependent Claim
141 words
8) A read-only memory device comprising a semiconductor substrate of a first conductivity type a plurality of first insulating films of increased film thicknesses formed in parallel stripes on the surface of said semiconductor substrate of the first conductivity type. an impurity region of a second conductivity type formed on said semiconductor substrate below said first insulating films, a plurality of second nsulating films of a film thickness lesser than that of said first insulating films, said second insulating films having formed between said first insulating films on the surface of said semiconductor substrate, and a plurality of electrode layers formed in a pattern of stripes extending parallel to one another in a direction substantially orthogonai to said first insulating films on said first insulating films, programming being made by selectively introducing impurities into the substrate surface below said electrode layers.
Claim 11
Dependent Claim
94 words
9) The read-only memory device according to claim 8, wherein said electrode layers comprise first electrode layers formed in a pattern of stripes extending parallel to one another in a direction substantially orthogonal to said first insulating films on said first insulating films and second electrode layers formed in a pattern of stripes extending parallel to one another in a direction substantially orthogonal to said first insulating films on said second insulating films in regions defined between adjacent first electrode layers, an interlayer insulating film being formed between said first and second electrode layers.
Claim 12
Dependent Claim
29 words
10) The read-only memory device according to claim 9 wherein the substrate surface below said second electrode layers is deeper than the substrate surface below said first electrode layers.
Claim 13
Dependent Claim
155 words
11) A method for producing a read-only memory device comprising the steps of forming oxidation resistant films having a pattern of parallel stripe on the surface of a semiconductor substrate of a first conductivity type, introducing impurities of a second conductivity type into the substrate surface in alignment with said oxidation resistant film, oxidizing the substrate surface, with said oxidation resistant film as the mask, to form first oxidized films of a large film thickness, removing said oxidation resistant films from said semi conductor surface, forming second oxidized films lesser in film thickness than said first oxidized films in regions on said substrate surface other than said first oxidized films forming electrode layers in a pattern of plural stripes extending on said second oxidized films parallel to one another in a direction substantially orthogonal to said first oxidized films, and selectively introducing impurities of a first conductivity type into substrate regions below said electrode layers.
Claim 14
Dependent Claim
155 words
11) A method for producing a read-only memory device comprising the steps of forming oxidation resistant films having a pattern of parallel stripe on the surface of a semiconductor substrate of a first conductivity type, introducing impurities of a second conductivity type into the substrate surface in alignment with said oxidation resistant film, oxidizing the substrate surface, with said oxidation resistant film as the mask, to form first oxidized films of a large film thickness, removing said oxidation resistant films from said semi conductor surface, forming second oxidized films lesser in film thickness than said first oxidized films in regions on said substrate surface other than said first oxidized films forming electrode layers in a pattern of plural stripes extending on said second oxidized films parallel to one another in a direction substantially orthogonal to said first oxidized films, and selectively introducing impurities of a first conductivity type into substrate regions below said electrode layers.
Claim 15
Dependent Claim
196 words
12) A method for producing a read-only memory comprising the steps of forming oxidation resistant films having a pattern of parallel stripes on the surface of a semiconductor substrate of a first conductivity type, introducing impurities of a second conductivity type into the substrate surface in alignment with said oxidation resistant film, oxidizing the substrate surface, with said oxidation resistant film as the mask, to form first oxidized films of a large film thickness, removing said oxidation resistant films from said semi conductor surface, forming second oxidized films lesser in film thickness than said first oxidized films in regions on said substrate surface other than said first oxidized films, forming electrode first layers in a pattern of plural stripes extending on said second oxidized films parallel to one another in a direction substantially orthogonal to said first oxidized films, forming an interlayer insulating film covering said first electrode layers, forming second electrode layers on said second oxidized films between said first electrode layers in a pattern of stripes parallel to said first electrode layers, and selectively introducing impurities of a first conductivity type into substrate regions below said first electrode layers and said second electrode layers.
Claim 16
Dependent Claim
196 words
12) A method for producing a read-only memory comprising the steps of forming oxidation resistant films having a pattern of parallel stripes on the surface of a semiconductor substrate of a first conductivity type, introducing impurities of a second conductivity type into the substrate surface in alignment with said oxidation resistant film, oxidizing the substrate surface, with said oxidation resistant film as the mask, to form first oxidized films of a large film thickness, removing said oxidation resistant films from said semi conductor surface, forming second oxidized films lesser in film thickness than said first oxidized films in regions on said substrate surface other than said first oxidized films, forming electrode first layers in a pattern of plural stripes extending on said second oxidized films parallel to one another in a direction substantially orthogonal to said first oxidized films, forming an interlayer insulating film covering said first electrode layers, forming second electrode layers on said second oxidized films between said first electrode layers in a pattern of stripes parallel to said first electrode layers, and selectively introducing impurities of a first conductivity type into substrate regions below said first electrode layers and said second electrode layers.
Claim 17
Dependent Claim
227 words
13) A method for producing a read-only memory device comprising the steps of forming oxidation resistant films having a pattern of parallel stripes on the surface of a semiconductor substrate of a first conductivity type, introducing impurities of a second conductivity type into the substrate surface in alignment with said oxidation resistant film, oxidizing the substrate surface, with said oxidation resistant film as the mask, to form first oxidized films of a large film thickness, removing said oxidation resistant films from said semiconductor surface forming second oxidized films lesser in film thickness than said first oxidized films in regions on said substrate surface other than said first oxidized films, selectively introducing impurities of a first conductivity type into substrate surface regions where first electrode layers are to be formed, forming a plurality of first electrode layers on said second oxidized films in a pattern of plural stripes extending parallel to one another in a direction substantially orthogonal to said first oxidized films, etching said second oxidized films and said substrate in alignment with said first electrode layers, selectively introducing impurities of a first conductivity type into surface region of the etched substrate, and forming second electrode layers in a pattern of stripes extending parallel to said first electrode layers on the etched substrate surface regions and the first electrode layers with the interposition of second oxidized films.
Claim 18
Dependent Claim
227 words
13) A method for producing a read-only memory device comprising the steps of forming oxidation resistant films having a pattern of parallel stripes on the surface of a semiconductor substrate of a first conductivity type, introducing impurities of a second conductivity type into the substrate surface in alignment with said oxidation resistant film, oxidizing the substrate surface, with said oxidation resistant film as the mask, to form first oxidized films of a large film thickness, removing said oxidation resistant films from said semiconductor surface forming second oxidized films lesser in film thickness than said first oxidized films in regions on said substrate surface other than said first oxidized films, selectively introducing impurities of a first conductivity type into substrate surface regions where first electrode layers are to be formed, forming a plurality of first electrode layers on said second oxidized films in a pattern of plural stripes extending parallel to one another in a direction substantially orthogonal to said first oxidized films, etching said second oxidized films and said substrate in alignment with said first electrode layers, selectively introducing impurities of a first conductivity type into surface region of the etched substrate, and forming second electrode layers in a pattern of stripes extending parallel to said first electrode layers on the etched substrate surface regions and the first electrode layers with the interposition of second oxidized films.
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