Patent EP0422672A1 successfully refreshed from Google Patents.
EP0422672A1
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EP
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Video signal noise reduction circuit
Assignee: Toshiba Corp
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Filing: 1990-10-12
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Granted: —
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Expires: 2010-10-12
Abstract
Abstract A first and a second video amplifiers (1, 4) of gain variable type are probided in the present invention. If it is defined that an output level the video signal is A, and input number (frame or field number) of the video pictures from the input starting time of the video signal is n , the gains (G1, G2) of the first and second video amplifiers (1, 4) are adjusted to A/n and (n - 1)A/n, respectively, for every video picture input. As a result, the output signal level can always be kept at a predetermined level, and the ideal noise reduction can be performed, since all signals added to every video picture input in the adder (2) are at the same level.
Inventors
- 👤 Teruo C/O Intell. Property Division Okada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 20:27
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/24; H; H04; H04N; H04N5/00; H04N5/14; H04N5/21
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
170 words
A noise reduction circuit for video signal, which comprises: first video amplifying means (1) of gain variable type for receiving the video signal; adding means (2) for receiving an output signal from said first video amplifying means (1) as one input signal thereof; one-picture delaying means (3) for receiving a signal branched from an output signal of the adding means (2) and outputting an output signal delayed by one picture; second video amplifying means (4) of gain variable type for receiving the delayed output signal from said one-picture delaying means (3) and supplying an output signal to said adding means (2) as the other input signal thereof; and gain control means (5) for adjusting a gain of said first video amplifying means (1) to A/n, and a gain of second video amplifying means (14) to (n - 1)A/n, for every video picture input, corresponding to an output level A of the video signal and input number n of said video pictures from the input starting time of the video signal.
Claim 2
Dependent Claim
170 words
A noise reduction circuit for video signal, which comprises: first video amplifying means (1) of gain variable type for receiving the video signal; adding means (2) for receiving an output signal from said first video amplifying means (1) as one input signal thereof; one-picture delaying means (3) for receiving a signal branched from an output signal of the adding means (2) and outputting an output signal delayed by one picture; second video amplifying means (4) of gain variable type for receiving the delayed output signal from said one-picture delaying means (3) and supplying an output signal to said adding means (2) as the other input signal thereof; and gain control means (5) for adjusting a gain of said first video amplifying means (1) to A/n, and a gain of second video amplifying means (14) to (n - 1)A/n, for every video picture input, corresponding to an output level A of the video signal and input number n of said video pictures from the input starting time of the video signal.
Claim 3
Dependent Claim
25 words
The noise reduction circuit according to claim 1, characterized in that said input number of said video pictures is frame number of said video signals.
Claim 4
Dependent Claim
25 words
The noise reduction circuit according to claim 1, characterized in that said input number of said video pictures is field number of said video signals.
References Cited (Backward Citations)
US4064530A
Cited
GB2122050A
Cited
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