Patent EP0420457A2 successfully refreshed from Google Patents.
EP0420457A2
Expired / Lapsed
EP
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Pipelined computer and methods in the same
Assignee: Panasonic Holdings Corp
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Filing: 1990-09-13
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Granted: —
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Expires: 2010-09-13
Abstract
Abstract An instruction is fed to the first and second pipelines at a same time. The instruction is advanced in the first pipeline. In addition, the instruction is advanced in the second pipeline. Advance of the instruction in the second pipeline is controlled in accordance with a position of the instruction in the first pipeline to synchronize advance of the instruction in the first pipeline and advance of the instruction in the second pipeline.
Inventors
- 👤 Hisakazu Edamatsu
- 👤 Hitoshi Yamashita
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 22:02
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3867; G06F9/3875; G06F9/3836; G06F9/3861; G06F9/3865; G06F9/3873; G06F9/3885; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
145 words
A method of synchronisation in a pipelined computer having a first instruction pipeline and a second instruction pipeline, the first instruction pipeline having "n" stages, the second instruction pipeline having "m" stages, the method comprising the steps of: feeding an instruction to the first instruction pipeline and the second instruction pipeline at the same time; advancing the instruction in the first instruction pipeline; advancing the instruction in the second instruction pipeline; and stopping advance of the instruction in a "j"-th stage of the second instruction pipeline until the instruction reaches an "i"-th stage of the first instruction pipeline to synchronise advance of the instruction in the first instruction pipeline and advance of the instruction in the second instruction pipeline at the "j"-th stage of the second instruction pipeline and the "i"-th stage of the first instruction pipeline, where "j" ≦ "m" and "i" ≦ "n".
Claim 2
Independent Claim
145 words
A method of synchronisation in a pipelined computer having a first instruction pipeline and a second instruction pipeline, the first instruction pipeline having "n" stages, the second instruction pipeline having "m" stages, the method comprising the steps of: feeding an instruction to the first instruction pipeline and the second instruction pipeline at the same time; advancing the instruction in the first instruction pipeline; advancing the instruction in the second instruction pipeline; and stopping advance of the instruction in a "j"-th stage of the second instruction pipeline until the instruction reaches an "i"-th stage of the first instruction pipeline to synchronise advance of the instruction in the first instruction pipeline and advance of the instruction in the second instruction pipeline at the "j"-th stage of the second instruction pipeline and the "i"-th stage of the first instruction pipeline, where "j" ≦ "m" and "i" ≦ "n".
Claim 3
Independent Claim
75 words
A method of disabling an instruction in a pipelined computer having a first instruction pipeline and a second instruction pipeline, the method comprising the steps of: detecting an exception by an instruction processed in the first instruction pipeline; determining whether or not the detected exception requires an instruction being processed in the second instruction pipeline to be disabled; and disabling the instruction in the second instruction pipeline according to the result of said determination step.
Claim 4
Independent Claim
75 words
A method of disabling an instruction in a pipelined computer having a first instruction pipeline and a second instruction pipeline, the method comprising the steps of: detecting an exception by an instruction processed in the first instruction pipeline; determining whether or not the detected exception requires an instruction being processed in the second instruction pipeline to be disabled; and disabling the instruction in the second instruction pipeline according to the result of said determination step.
Claim 5
Independent Claim
241 words
A method of synchronisation in a pipelined computer having a first instruction pipeline, a second instruction pipeline, and a third instruction pipeline, the first instruction pipeline having "n" stages, the second instruction pipeline having "m" stages, the third instruction pipeline having "k" stages, the method comprising the steps of: feeding an instruction to the first instruction pipeline, the second instruction pipeline, and the third instruction pipeline at the same time; advancing the instruction in the first instruction pipeline; advancing the instruction in the second instruction pipeline; advancing the instruction in the third instruction pipeline; stopping advance of the instruction in a "j"-th stage of the second instruction pipeline until the instruction reaches an "i"-th stage of the first instruction pipeline to synchronise advance of the instruction in the first instruction pipeline and advance of the instruction in the second instruction pipeline at the "j"-th stage of the second instruction pipeline and the "i"-th stage of the first instruction pipeline, where "j" ≦ "m" and "i" ≦ "n"; and stopping advance of the instruction in a "y"-th stage of the third instruction pipeline until the instruction reaches an "x"-th stage of the first instruction pipeline to synchronise advance of the instruction in the first instruction pipeline and advance of the instruction in the third instruction pipeline at the "y"-th stage of the third instruction pipeline and the "x"-th stage of the first instruction pipeline, where "y" ≦ "k" and "x" ≦ "n".
Claim 6
Independent Claim
241 words
A method of synchronisation in a pipelined computer having a first instruction pipeline, a second instruction pipeline, and a third instruction pipeline, the first instruction pipeline having "n" stages, the second instruction pipeline having "m" stages, the third instruction pipeline having "k" stages, the method comprising the steps of: feeding an instruction to the first instruction pipeline, the second instruction pipeline, and the third instruction pipeline at the same time; advancing the instruction in the first instruction pipeline; advancing the instruction in the second instruction pipeline; advancing the instruction in the third instruction pipeline; stopping advance of the instruction in a "j"-th stage of the second instruction pipeline until the instruction reaches an "i"-th stage of the first instruction pipeline to synchronise advance of the instruction in the first instruction pipeline and advance of the instruction in the second instruction pipeline at the "j"-th stage of the second instruction pipeline and the "i"-th stage of the first instruction pipeline, where "j" ≦ "m" and "i" ≦ "n"; and stopping advance of the instruction in a "y"-th stage of the third instruction pipeline until the instruction reaches an "x"-th stage of the first instruction pipeline to synchronise advance of the instruction in the first instruction pipeline and advance of the instruction in the third instruction pipeline at the "y"-th stage of the third instruction pipeline and the "x"-th stage of the first instruction pipeline, where "y" ≦ "k" and "x" ≦ "n".
Claim 7
Independent Claim
127 words
A method of disabling an instruction in a pipelined computer having a first instruction pipeline, a second instruction pipeline, and a third instruction pipeline, the method comprising the steps of: detecting an exception by an instruction processed in the first instruction pipeline; determining whether or not the detected exception requires the instruction being processed in the second instruction pipeline to be disabled; disabling the instruction in the second instruction pipeline according to the result of the determination step related to the second instruction pipeline; determining whether or not the detected exception requires an instruction being processed in the third instruction pipeline to be disabled; and disabling the instruction in the third instruction pipeline according to the result of the determining step related to the third instruction pipeline.
Claim 8
Independent Claim
127 words
A method of disabling an instruction in a pipelined computer having a first instruction pipeline, a second instruction pipeline, and a third instruction pipeline, the method comprising the steps of: detecting an exception by an instruction processed in the first instruction pipeline; determining whether or not the detected exception requires the instruction being processed in the second instruction pipeline to be disabled; disabling the instruction in the second instruction pipeline according to the result of the determination step related to the second instruction pipeline; determining whether or not the detected exception requires an instruction being processed in the third instruction pipeline to be disabled; and disabling the instruction in the third instruction pipeline according to the result of the determining step related to the third instruction pipeline.
Claim 9
Independent Claim
220 words
A method of synchronisation in a pipelined computer having a first instruction pipeline and a second instruction pipeline, the first instruction pipeline having "n" stages, the second instruction pipeline having "m" stages, the method comprising the steps of: feeding an instruction to the first instruction pipeline and the second instruction pipeline at the same time; advancing the instruction in the first instruction pipeline; and advancing the instruction in the second instruction pipeline; either stopping advance of the instruction in a "j"-th stage of the second instruction pipeline until the instruction reaches an "i"-th stage of the first instruction pipeline to synchronise advance of the instruction in the first instruction pipeline and advance of the instruction in the second instruction pipeline at the "j"-th stage of the second instruction pipeline and the "i"-th stage of the first instruction pipeline, where "j" ≦ "m" and "i" ≦ "n"; or stopping advance of the instruction in a "p"-th stage of the first instruction pipeline until the instruction reaches a "q"-th stage of the second instruction pipeline to synchronise advance of the instruction in the first instruction pipeline and advance of the instruction in the second instruction pipeline at the "p"-th stage of the first instruction pipeline and the "q"-th stage of the second instruction pipeline, where "p" ≦ "n" and "q" ≦ "m".
Claim 10
Independent Claim
220 words
A method of synchronisation in a pipelined computer having a first instruction pipeline and a second instruction pipeline, the first instruction pipeline having "n" stages, the second instruction pipeline having "m" stages, the method comprising the steps of: feeding an instruction to the first instruction pipeline and the second instruction pipeline at the same time; advancing the instruction in the first instruction pipeline; and advancing the instruction in the second instruction pipeline; either stopping advance of the instruction in a "j"-th stage of the second instruction pipeline until the instruction reaches an "i"-th stage of the first instruction pipeline to synchronise advance of the instruction in the first instruction pipeline and advance of the instruction in the second instruction pipeline at the "j"-th stage of the second instruction pipeline and the "i"-th stage of the first instruction pipeline, where "j" ≦ "m" and "i" ≦ "n"; or stopping advance of the instruction in a "p"-th stage of the first instruction pipeline until the instruction reaches a "q"-th stage of the second instruction pipeline to synchronise advance of the instruction in the first instruction pipeline and advance of the instruction in the second instruction pipeline at the "p"-th stage of the first instruction pipeline and the "q"-th stage of the second instruction pipeline, where "p" ≦ "n" and "q" ≦ "m".
Claim 11
Independent Claim
153 words
A method of disabling an instruction in a pipelined computer having a first instruction pipeline and a second instruction pipeline, the method comprising the steps of: either detecting an exception by an instruction processed in the first instruction pipeline; determining whether or not the detected exception by the instruction in the first instruction pipeline requires an instruction being processed in the second instruction pipeline to be disabled; and disabling the instruction in the second instruction pipeline according to the result of the determination step related to the second instruction pipeline; or detecting an exception by an instruction processed in the second instruction pipeline; determining whether or not the detected exception by the instruction in the second instruction pipeline requires an instruction processed in the first instruction pipeline to be disabled; and disabling the instruction in the first instruction pipeline according to the result of the determination step related to the first instruction pipeline.
Claim 12
Independent Claim
153 words
A method of disabling an instruction in a pipelined computer having a first instruction pipeline and a second instruction pipeline, the method comprising the steps of: either detecting an exception by an instruction processed in the first instruction pipeline; determining whether or not the detected exception by the instruction in the first instruction pipeline requires an instruction being processed in the second instruction pipeline to be disabled; and disabling the instruction in the second instruction pipeline according to the result of the determination step related to the second instruction pipeline; or detecting an exception by an instruction processed in the second instruction pipeline; determining whether or not the detected exception by the instruction in the second instruction pipeline requires an instruction processed in the first instruction pipeline to be disabled; and disabling the instruction in the first instruction pipeline according to the result of the determination step related to the first instruction pipeline.
Claim 13
Dependent Claim
117 words
A pipelined computer comprising: a first instruction pipeline having a plurality of stages; a second instruction pipeline having a plurality of stages; a first instruction pipeline controller for controlling the first instruction pipeline; a second instruction pipeline controller for controlling the second instruction pipeline; a first condition holding device including condition temporarily-holding devices provided in the stages of the second instruction pipeline, and a condition generator generating a condition of the first instruction pipeline each time the first instruction pipeline advances; and means for monitoring the advance of the first instruction pipeline via the condition holding device, and for controlling advance of the second instruction pipeline in response to the monitored advance of the first instruction pipeline.
Claim 14
Dependent Claim
117 words
A pipelined computer comprising: a first instruction pipeline having a plurality of stages; a second instruction pipeline having a plurality of stages; a first instruction pipeline controller for controlling the first instruction pipeline; a second instruction pipeline controller for controlling the second instruction pipeline; a first condition holding device including condition temporarily-holding devices provided in the stages of the second instruction pipeline, and a condition generator generating a condition of the first instruction pipeline each time the first instruction pipeline advances; and means for monitoring the advance of the first instruction pipeline via the condition holding device, and for controlling advance of the second instruction pipeline in response to the monitored advance of the first instruction pipeline.
Claim 15
Dependent Claim
103 words
A pipelined computer according to claim 7, further comprising: a third instruction pipeline having a plurality of stages; a third instruction pipeline controller for controlling the third instruction pipeline; a second condition holding device including condition temporarily-holding devices provided in the stages of the third instruction pipeline, and a condition generator generating a condition of the first instruction pipeline each time the first instruction pipeline advances; and means for monitoring the advance of the first instruction pipeline via the second condition holding device, and for controlling advance of the third instruction pipeline in response to the monitored advance of the first instruction pipeline.
Claim 16
Dependent Claim
32 words
A pipelined computer according to claim 7 or 8, wherein the or each of the condition holding devices comprises a counter device including a counter circuit and a count value temporarily-holding circuit.
Claim 17
Dependent Claim
16 words
A pipelined computer according to claim 9, wherein the counter circuit comprises a down counter circuit.
Claim 18
Dependent Claim
163 words
A pipelined computer comprising: a first instruction pipeline having a plurality of stages; a second instruction pipeline having a plurality of stages; a first instruction pipeline controller for controlling the first instruction pipeline; a second instruction pipeline controller for controlling the second instruction pipeline; a first condition holding device including condition temporarily-holding devices provided in the stages of the second instruction pipeline, and a condition generator generating a condition of the first instruction pipeline each time the first instruction pipeline advances; an exception detector for detecting an exception by an instruction processed in the first instruction pipeline; a first determination section for determining whether or not an instruction processed in the second instruction pipeline should be disabled according to the detected exception and a value of at least one of the condition temporarily-holding devices of the first condition holding device; and means for disabling the instruction in the second instruction pipeline according to the result of said determination by the first determination section.
Claim 19
Dependent Claim
163 words
A pipelined computer comprising: a first instruction pipeline having a plurality of stages; a second instruction pipeline having a plurality of stages; a first instruction pipeline controller for controlling the first instruction pipeline; a second instruction pipeline controller for controlling the second instruction pipeline; a first condition holding device including condition temporarily-holding devices provided in the stages of the second instruction pipeline, and a condition generator generating a condition of the first instruction pipeline each time the first instruction pipeline advances; an exception detector for detecting an exception by an instruction processed in the first instruction pipeline; a first determination section for determining whether or not an instruction processed in the second instruction pipeline should be disabled according to the detected exception and a value of at least one of the condition temporarily-holding devices of the first condition holding device; and means for disabling the instruction in the second instruction pipeline according to the result of said determination by the first determination section.
Claim 20
Dependent Claim
133 words
A pipelined computer according to claim 11, further comprising: a third instruction pipeline having a plurality of stages; a third instruction pipeline controller for controlling the third instruction pipeline; a second condition holding device including condition temporarily-holding devices provided in the stages of the third instruction pipeline, and a condition generator generating a condition of the first instruction pipeline each time the first instruction pipeline advances; a second determination section for determining whether or not an instruction processed in the third instruction pipeline should be disabled according to the detected exception and a value of at least one of the condition temporarily-holding devices in the second condition holding device; and means for disabling the instruction in the third instruction pipeline in response to a result of said judging by the second judgement section.
Claim 21
Dependent Claim
185 words
A pipelined computer comprising: a first instruction pipeline having a plurality of stages; a second instruction pipeline having a plurality of stages; a first instruction pipeline controller for controlling the first instruction pipeline; a second instruction pipeline controller for controlling the second instruction pipeline; a first condition holding device including condition temporarily-holding devices provided in the stages of the first instruction pipeline, and a condition generator for generating a condition each time the second instruction pipeline advances; and a second condition holding device including condition temporarily-holding devices provided in the stages of the second instruction pipeline, and a condition generator for generating a condition each time the first instruction pipeline advances; either means for monitoring the advance of the first instruction pipeline via the second condition holding device, and for controlling advance of the second instruction pipeline in response to the monitored advance of the first instruction pipeline; or means for monitoring the advance of the second instruction pipeline via the first condition holding device, and for controlling advance of the first instruction pipeline in response to the monitored advance of the second instruction pipeline.
Claim 22
Dependent Claim
185 words
A pipelined computer comprising: a first instruction pipeline having a plurality of stages; a second instruction pipeline having a plurality of stages; a first instruction pipeline controller for controlling the first instruction pipeline; a second instruction pipeline controller for controlling the second instruction pipeline; a first condition holding device including condition temporarily-holding devices provided in the stages of the first instruction pipeline, and a condition generator for generating a condition each time the second instruction pipeline advances; and a second condition holding device including condition temporarily-holding devices provided in the stages of the second instruction pipeline, and a condition generator for generating a condition each time the first instruction pipeline advances; either means for monitoring the advance of the first instruction pipeline via the second condition holding device, and for controlling advance of the second instruction pipeline in response to the monitored advance of the first instruction pipeline; or means for monitoring the advance of the second instruction pipeline via the first condition holding device, and for controlling advance of the first instruction pipeline in response to the monitored advance of the second instruction pipeline.
Claim 23
Dependent Claim
31 words
A pipelined computer according to claim 13, wherein each of the first and second condition holding devices comprises a counter device including a counter circuit and a count value temporarily-holding circuit.
Claim 24
Dependent Claim
16 words
A pipelined computer according to claim 14, wherein the counter circuit comprises a down counter circuit.
Claim 25
Dependent Claim
289 words
A pipelined computer comprising: a first instruction pipeline having a plurality of stages; a second instruction pipeline having a plurality of stages; a first instruction pipeline controller for controlling the first instruction pipeline; a second instruction pipeline controller for controlling the second instruction pipeline; a first condition holding device including condition temporarily-holding devices provided in the stages of the first instruction pipeline, and a condition generator for generating a condition each time the second instruction pipeline advances; a second condition holding device including condition temporarily-holding devices provided in the stages of the second instruction pipeline, and a condition generator for generating a condition each time the first instruction pipeline advances; a first exception detector for detecting an exception by an instruction processed in the first instruction pipeline; and a second exception detector for detecting an exception by an instruction processed in the second instruction pipeline; either a first determination section for determining whether or not an instruction processed in the first instruction pipeline should be disabled according to the exception detected by the second exception detector and a value of at least one of the condition temporarily-holding devices in the first condition holding device; and means for disabling the instruction in the first instruction pipeline according to the result of the determination by the first determination section; or a second determination section for determining whether or not an instruction processed in the second instruction pipeline should be disabled according to the exception detected by the first exception detector and a value of at least one of the condition temporarily-holding devices in the second condition holding device; and means for disabling the instruction in the second instruction pipeline according to the result of the determination by the second determination section.
Claim 26
Dependent Claim
289 words
A pipelined computer comprising: a first instruction pipeline having a plurality of stages; a second instruction pipeline having a plurality of stages; a first instruction pipeline controller for controlling the first instruction pipeline; a second instruction pipeline controller for controlling the second instruction pipeline; a first condition holding device including condition temporarily-holding devices provided in the stages of the first instruction pipeline, and a condition generator for generating a condition each time the second instruction pipeline advances; a second condition holding device including condition temporarily-holding devices provided in the stages of the second instruction pipeline, and a condition generator for generating a condition each time the first instruction pipeline advances; a first exception detector for detecting an exception by an instruction processed in the first instruction pipeline; and a second exception detector for detecting an exception by an instruction processed in the second instruction pipeline; either a first determination section for determining whether or not an instruction processed in the first instruction pipeline should be disabled according to the exception detected by the second exception detector and a value of at least one of the condition temporarily-holding devices in the first condition holding device; and means for disabling the instruction in the first instruction pipeline according to the result of the determination by the first determination section; or a second determination section for determining whether or not an instruction processed in the second instruction pipeline should be disabled according to the exception detected by the first exception detector and a value of at least one of the condition temporarily-holding devices in the second condition holding device; and means for disabling the instruction in the second instruction pipeline according to the result of the determination by the second determination section.
Claim 27
Dependent Claim
98 words
A pipelined computer comprising: first and second instruction pipelines; means for feeding an instruction to the first and second pipelines at the same time; means for advancing the instruction in the first pipeline; means for advancing the instruction in the second pipeline; means for detecting the position of the instruction in the first pipeline; and means for controlling advance of the instruction in the second pipeline in accordance with the detected position of the instruction in the first pipeline to synchronise advance of the instruction in the first pipeline and advance of the instruction in the second pipeline.
Claim 28
Dependent Claim
98 words
A pipelined computer comprising: first and second instruction pipelines; means for feeding an instruction to the first and second pipelines at the same time; means for advancing the instruction in the first pipeline; means for advancing the instruction in the second pipeline; means for detecting the position of the instruction in the first pipeline; and means for controlling advance of the instruction in the second pipeline in accordance with the detected position of the instruction in the first pipeline to synchronise advance of the instruction in the first pipeline and advance of the instruction in the second pipeline.
Claim 29
Dependent Claim
77 words
A pipelined computer comprising: first and second instruction pipelines; means for feeding instructions to the first and second pipelines at a same time; means for advancing the instructions in the first pipeline; means for advancing the instructions in the second pipeline; means for detecting an exception by at least one of the instructions in the first pipeline; and means for disabling at least one of the instructions in the second pipeline in response to the detected exception.
Claim 30
Dependent Claim
77 words
A pipelined computer comprising: first and second instruction pipelines; means for feeding instructions to the first and second pipelines at a same time; means for advancing the instructions in the first pipeline; means for advancing the instructions in the second pipeline; means for detecting an exception by at least one of the instructions in the first pipeline; and means for disabling at least one of the instructions in the second pipeline in response to the detected exception.
References Cited (Backward Citations)
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