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EP0419226A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Signal processing circuit of a bar code reader

Assignee: Fujitsu Ltd
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Filing: 1990-09-19
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Granted: —
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Expires: 2010-09-19
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Abstract

Abstract A signal processing circuit includes: a signal input unit (30) for optically detecting a bar code and outputting a first signal; a differential unit (D) connected to the signal input unit (30), for amplifying the first signal, differentiating the first signal, filtering the first signal and outputting a second signal; a comparison unit (C) connected to the differential unit (D), for integrating the second signal and outputting a third signal, and comparing the second signal with the third signal and outputting a fourth signal; a slice level generation unit (S) connected to the differential unit (D), for holding a peak voltage of the second signal; a gate signal output unit (G) connected to the differential unit (D) and the slice level generation unit (S), for comparing the second signal with the positive slice voltage and the negative slice voltage; and a signal output unit (OUT) connected to the comparison unit (C) and the gate signal output unit (G), for inputting the fourth signal and the positive slice voltage, and outputting a gate signal to obtain a binary-coded signal.

Inventors

  • 👤 Shinichi Sato

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-08 08:03
CPC Classifications
G; G06; G06K; G06K7/00; G06K7/10; G06K7/10544; G06K7/10821; G06K7/10851

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 248 words
A signal processing circuit of a bar code reader, comprising: signal input means for optically detecting a bar code provided on a surface of goods and outputting a first signal after optical-to-electrical conversion; differential means connected to the signal input means, for amplifying the first signal, differentiating the first signal, filtering the first signal after differentiation to eliminate high frequency noise, and outputting a second signal after filtering; comparison means connected to the differential means, for integrating the second signal and outputting a third signal after integration, and comparing the second signal with the third signal and outputting a fourth signal when the third signal is larger than the second signal; slice level generation means connected to the differential means, for holding a peak voltage of the second signal, suppressing the peak voltage to a predetermined upper limitation voltage, discharging the suppressed peak voltage in accordance with a predeter­mined time constant, and dividing the suppressed peak voltage into a predetermined voltage rate to obtain a positive slice voltage and a negative slice voltage; gate signal output means connected to the differential means and the slice level generation means, for comparing the second signal with the positive slice voltage and the negative slice voltage; and signal output means connected to the comparison means and the gate signal output means, for inputting the fourth signal and the positive slice voltage, inputting the inverted fourth signal and the negative slice voltage, and outputting a gate signal to obtain a binary-coded signal.
Claim 2
Dependent Claim 248 words
A signal processing circuit of a bar code reader, comprising: signal input means for optically detecting a bar code provided on a surface of goods and outputting a first signal after optical-to-electrical conversion; differential means connected to the signal input means, for amplifying the first signal, differentiating the first signal, filtering the first signal after differentiation to eliminate high frequency noise, and outputting a second signal after filtering; comparison means connected to the differential means, for integrating the second signal and outputting a third signal after integration, and comparing the second signal with the third signal and outputting a fourth signal when the third signal is larger than the second signal; slice level generation means connected to the differential means, for holding a peak voltage of the second signal, suppressing the peak voltage to a predetermined upper limitation voltage, discharging the suppressed peak voltage in accordance with a predeter­mined time constant, and dividing the suppressed peak voltage into a predetermined voltage rate to obtain a positive slice voltage and a negative slice voltage; gate signal output means connected to the differential means and the slice level generation means, for comparing the second signal with the positive slice voltage and the negative slice voltage; and signal output means connected to the comparison means and the gate signal output means, for inputting the fourth signal and the positive slice voltage, inputting the inverted fourth signal and the negative slice voltage, and outputting a gate signal to obtain a binary-coded signal.
Claim 3
Dependent Claim 92 words
A signal processing circuit as claimed in claim 1, wherein the slice level generation means comprises a peak hold circuit for receiving the second signal and holding the peak voltage of the second signal, an upper limitation circuit connected to the peak hold circuit for receiving an output of the peak hold circuit and suppressing the peak voltage to the predetermined upper limitation voltage, and a discharge circuit connected to the upper limitation circuit for discharging the peak voltage suppressed by the upper limitation circuit in accordance with the predetermined time constant.
Claim 4
Dependent Claim 25 words
A signal processing circuit as claimed in claim 1 or 2, wherein the predetermined voltage rate is determined to half of the upper limitation voltage.
Claim 5
Dependent Claim 45 words
A signal processing circuit as claimed in claim 2 or 3, wherein the upper limitation circuit comprises an operational amplifier to reduce the peak voltage when the peak voltage exceeds the predetermined upper limitation voltage, and a variable resistor to determine the upper limitation voltage.

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