Patent EP0419128A1 successfully refreshed from Google Patents.
EP0419128A1
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EP
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Silicon MOSFET doped with germanium to increase lifetime of operation
Assignee: AT&T Inc
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Filing: 1990-09-13
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Granted: —
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Expires: 2010-09-13
Abstract
Abstract In order to reduce the rate of (hot charge-carrier) degradation of semiconductor devices formed in a semiconductor body (10), a neutral impurity--such as germanium in silicon MOS transistors--is introduced into the body in a neighborhood of an intersection of a p-n junction (10-15) with a surface (10.5) of the body.
Inventors
- 👤 Kwok Kwok Ng
- 👤 Chien-Shing Pai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 05:30
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/80; H10D62/83; H10D62/834; H10P30/208
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
158 words
In an integrated circuit incorporated at a major surface (10.5) of semiconductor body (10), a device comprising a p-n junction (10-15) which intersects the surface of the semiconductor body, the junction being formed by the interface of first (15) and second (10) regions of the semiconductor body, the first and second regions having first and second conductivity types, respectively, owing to respective first and second concentrations of conductivity-type determining impurities of the first and second types, the first concentration at the p-n junction being higher than the second thereat, characterized in that a portion (16, 26, 36) of the second region (10) which is contiguous with at least one-half the intersection of the p-n junction (10-15) with the surface of the semiconductor body everywhere contains a concentration of neutral impurities which is at least as high as the second concentration in the second region at the intersection of the p-n junction with the surface of the semiconductor body.
Claim 2
Dependent Claim
158 words
In an integrated circuit incorporated at a major surface (10.5) of semiconductor body (10), a device comprising a p-n junction (10-15) which intersects the surface of the semiconductor body, the junction being formed by the interface of first (15) and second (10) regions of the semiconductor body, the first and second regions having first and second conductivity types, respectively, owing to respective first and second concentrations of conductivity-type determining impurities of the first and second types, the first concentration at the p-n junction being higher than the second thereat, characterized in that a portion (16, 26, 36) of the second region (10) which is contiguous with at least one-half the intersection of the p-n junction (10-15) with the surface of the semiconductor body everywhere contains a concentration of neutral impurities which is at least as high as the second concentration in the second region at the intersection of the p-n junction with the surface of the semiconductor body.
Claim 3
Dependent Claim
40 words
The method of making the device recited in claim 1 in which an annealing of the body is performed after introduction into the body of the neutral impurities but before introduction into the body of the first conductivity-type determining impurities.
Claim 4
Dependent Claim
42 words
In an integrated circuit, the device of claim 1 in which the portion of the second region laterally extends, at the surface of the body from intersection of the junction into the second region, for a distance of at least 0.01 micrometer.
Claim 5
Dependent Claim
51 words
In an integrated circuit, the device of claim 1 in which the first region of the device is the drain region of an MOS transistor, and in which the portion of the second region is contiguous with substantially the entire intersection of the p-n junction with the surface of the body.
Claim 6
Dependent Claim
75 words
In an integrated circuit, the device of claim 1 in which the first region of the device is the drain region of a silicon MOS transistor device having a channel contiguous with the drain region, in which the concentration of neutral impurities is at least 3x10¹⁷ germanium atoms or ions per cubic centimeter, and in which such concentration extends laterally beyond the drain region into the channel for a distance of at least 0.01 micrometers.
Claim 7
Dependent Claim
26 words
In an integrated circuit, the device of claim 5 in which an insulator layer overlies the surface of the body where the p-n junction intersects it.
Claim 8
Dependent Claim
26 words
In an integrated circuit, the device of claim 4 in which an insulator layer overlies the surface of the body where the p-n junction intersects it.
Claim 9
Dependent Claim
26 words
In an integrated circuit, the device of claim 1 in which an insulator layer overlies the surface of the body where the p-n junction intersects it.
Claim 10
Dependent Claim
26 words
In an integrated circuit, a device according to claim 1 in which the first region of the device is the drain region of an MOS transistor.
Claim 11
Dependent Claim
29 words
In an integrated circuit, a device made in accordance with claim 2 in which an insulator layer overlies the surface of the body where the p-n junction intersects it.
Claim 12
Dependent Claim
10 words
An integrated circuit comprising the device recited in claim 1.
Claim 13
Dependent Claim
27 words
An integrated circuit comprising the device recited in claim 1 in which an insulator layer overlies the surface of the body where the p-n junction intersects it.
Claim 14
Dependent Claim
40 words
The method of making the device recited in claim 4 in which an annealing of the body is performed after introduction into the body of the neutral impurities but before introduction into the body of the first conductivity-type determining impurities.
References Cited (Backward Citations)
EP0176409A2
Cited
US4837173A
Cited
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