Patent EP0419112A2 successfully refreshed from Google Patents.
EP0419112A2
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EP
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Serial data transmission
Assignee: Psion Holdings Ltd
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Filing: 1990-09-11
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Granted: —
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Expires: 2010-09-11
Abstract
Abstract A serial data interface communicates data between a control processor (1) and one or more slave processors (2) via a serial bus (3). Typically the control processor (1) may be formed in a hand held or lap top computer and the slave processor (2) in a peripheral device for the computer. The control processor (1) transmits a clock signal over a clock line in the serial bus (3) to the slave processor (2). At the same time, control or data frames are transmitted from the control processor (1) to the slave processor (2) or data frames are transmitted from the slave processor (2) to the control processor (1). Each data frame has a control portion which indentifies the frame as a control frame or as a data frame, and following the control portion a plurality of data bits bounded by idle bits. Both the slave processor (2) and the control processor (1) free the data line for a change in the direction of data transmission during each idle bit. In a preferred example, each control frame includes as one of its data bits a select bit identifying the control frame as a slave select frame or as a slave control frame. Each slave select frame includes as a further one of its data bits a reset bit. When the reset bit takes one pre-determined value the transmission of the slave select frame to the slave processor (2) causes that processor to reset to a pre-determined state. Otherwise, the transmission of the slave select frame to the slave processor selects or de-selects the slave processor. Each slave control frame includes as one or more of its data bits data transmission parameters which set the slave processor (2) to read or write one or more data frames subsequent to the current control frame.
Inventors
- 👤 Nicholas Simon Myers
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 06:51
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4282; G06F13/4291
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
147 words
A method of communicating data between a control processor (1) and a slave processor (2) over a serial interface (3) comprising a bi-directional data line (DATA) and a uni-directional clock line (CK), comprising: transmitting a clock signal from the control processor (1) over the clock line (CK) to the slave processor (2), and at the same time transmitting control or data frames from the control processor (1) to the slave processor (2) or transmitting data frames from the slave processor (2) to the control processor (1); each frame comprising a control portion (CTRL) to identify a frame as a control frame or as a data frame, and following the control portion a plurality of data bits (D0-D7) bounded by idle bits (I1, I2), both the slave and the control processor freeing the data line for a change in the direction of data transmission during each idle bit.
Claim 2
Independent Claim
147 words
A method of communicating data between a control processor (1) and a slave processor (2) over a serial interface (3) comprising a bi-directional data line (DATA) and a uni-directional clock line (CK), comprising: transmitting a clock signal from the control processor (1) over the clock line (CK) to the slave processor (2), and at the same time transmitting control or data frames from the control processor (1) to the slave processor (2) or transmitting data frames from the slave processor (2) to the control processor (1); each frame comprising a control portion (CTRL) to identify a frame as a control frame or as a data frame, and following the control portion a plurality of data bits (D0-D7) bounded by idle bits (I1, I2), both the slave and the control processor freeing the data line for a change in the direction of data transmission during each idle bit.
Claim 3
Dependent Claim
142 words
A method according to claim 1, in which each control frame includes as one of its data bits (D0-D7) a select bit which identifies the control frame as a slave select frame or as a slave control frame; each slave select frame including as a further one of its data bits a reset bit, when the reset bit takes one predetermined value the transmission of the slave select frame to the slave processor (2) causing the slave processor (2) to reset to a predetermined state otherwise the transmission of the slave select frame to the slave processor (2) selecting or de-selecting the slave processor (2); each slave control frame including as one or more of its data bits data transmission parameters to set the slave processor (2) to read or write one or more data frames subsequent to the current control frame.
Claim 4
Dependent Claim
58 words
A method according to claim 2, in which the transmission parameters for the slave control frame include a read/write bit to determine whether the slave processor reads or writes data in the succeeding data frame and a single/multi bit to determine whether the slave transmits or receives single or multiple units of data in the subsequent data frames.
Claim 5
Dependent Claim
63 words
A method according to claim 2 or 3, in which the data bits of the slave select frame include an identification field, the slave processor (2) being assigned a unique identification number, the slave processor (2) in response to any slave select frame including its unique identification number subsequently transmitting to the control processor (1) a data frame including a predetermined information field.
Claim 6
Dependent Claim
42 words
A method according to claim 4, in which the control processor (1) adjusts the rate of the clock output to the maximum rate compatible with a particular slave processor (2) in response to the information field received from the slave processor (2).
Claim 7
Independent Claim
267 words
A system for communicating serial data comprising; a control processor (1); a slave processor (2); and and a serial interface (3) linking the control processor to the slave processor, the serial interface comprising a bi-directional data line (DATA) and a uni-directional clock line (CK), the control processor including clock means arranged to transmit a clock signal over the clock line (CK) to the slave processor (2) while at the same time the control processor (1) transmits control or data frames to the slave processor (2) or receives data frames transmitted from the slave processor (2); the control processor (1) including transmitting means arranged to transmit control frames and data frames onto the interface and reading means arranged to read data frames from the interface; the slave processor including transmitting means arranged to transmit data frames onto the interface and reading means arranged to read control frames and data frames from the interface; the transmitting means and reading means being arranged to transmit and read respectively frames comprising a control portion (CTRL) identifying a frame as a control frame or as a data frame, and following the control portion a plurality of data bits (D0-D7) bounded by idle bits (I1, I2), both the slave (2) and the control processor (1) freeing the data line for a change in the direction of data transmission during each idle bit, (I1, I2) the slave processor (2) being arranged to receive the clock signal from the clock line and to synchronise the operation of the slave processor transmitting and reading means with the control processor (1) in response to the clock signal.
Claim 8
Independent Claim
267 words
A system for communicating serial data comprising; a control processor (1); a slave processor (2); and and a serial interface (3) linking the control processor to the slave processor, the serial interface comprising a bi-directional data line (DATA) and a uni-directional clock line (CK), the control processor including clock means arranged to transmit a clock signal over the clock line (CK) to the slave processor (2) while at the same time the control processor (1) transmits control or data frames to the slave processor (2) or receives data frames transmitted from the slave processor (2); the control processor (1) including transmitting means arranged to transmit control frames and data frames onto the interface and reading means arranged to read data frames from the interface; the slave processor including transmitting means arranged to transmit data frames onto the interface and reading means arranged to read control frames and data frames from the interface; the transmitting means and reading means being arranged to transmit and read respectively frames comprising a control portion (CTRL) identifying a frame as a control frame or as a data frame, and following the control portion a plurality of data bits (D0-D7) bounded by idle bits (I1, I2), both the slave (2) and the control processor (1) freeing the data line for a change in the direction of data transmission during each idle bit, (I1, I2) the slave processor (2) being arranged to receive the clock signal from the clock line and to synchronise the operation of the slave processor transmitting and reading means with the control processor (1) in response to the clock signal.
Claim 9
Dependent Claim
142 words
A system according to claim 6, in which each control frame includes as one of its data bits (D0-D7) a select bit which identifies the control frame as a slave select frame or as a slave control frame; each slave select frame including as a further one of its data bits (D0-D7) a reset bit, the slave processor (2) being arranged to reset to a predetermined state when the reset bit takes one predetermined value, and otherwise to be selected or de-selected in response to the reading of a slave select frame by the slave processor reading means; each slave control frame including as one or more of its data bits (D0-D7) data transmission parameters, the slave processor being set in response to the data transmission parameters to read or write one or more data frames subsequent to the current control frame.
Claim 10
Dependent Claim
77 words
A system according to claim 7, in which the transmission parameters for the slave control frame include a read/write bit, the slave processor being arranged to read or write data in the succeeding data frame according to the value of the read/write bit; and a single/multi bit, the slave processor being arranged to read or write single or multiple units of data in the subsequent data frame or frames according to the value of the single/multi bit.
Claim 11
Dependent Claim
74 words
A system according to claim 7 or 8, in which the data bits of the slave select frame include an identification field, the slave processor (2) connected to the interface (3) including means to store a unique identification number and being arranged in response to any slave select frame including as its identification field the said unique identification number subsequently to transmit to the control processor a data frame including a pre-determined information field.
Claim 12
Dependent Claim
49 words
A system according to claim 9, in which the clock means are variable and the control processor is arranged to adjust the rate of the clock to the maximum rate compatible with a particular slave processor (2) in response to the information field received from that slave processor (2).
Claim 13
Dependent Claim
17 words
A control processor (1) adapted for use in a system according to any one of claims 6-10.
Claim 14
Dependent Claim
16 words
A slave processor (2) adapted for use in a system according to anyone of claims 6-10.
Claim 15
Dependent Claim
15 words
A hand held or lap top computer including a control processor according to claim 11.
Claim 16
Dependent Claim
18 words
A peripheral for a hand held or lap top computer including a slave processor according to claim 12.
Claim 17
Dependent Claim
15 words
A peripheral according to claim 14, in which the peripheral is a mass storage device.
Claim 18
Dependent Claim
15 words
A peripheral according to claim 15 in which the mass storage device includes an FE²PROM.
Claim 19
Dependent Claim
40 words
A peripheral device according to claim 15 further comprising means (9) electrically connected between the serial interface (3) and the FE²PROM for applying an erase voltage to the FE²PROM in response to a control signal from the slave processor (2).
References Cited (Backward Citations)
No citation records indexed.
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