Patent EP0416903A2 successfully refreshed from Google Patents.
EP0416903A2
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Method of fabricating a programmable interconnect structure
Assignee: QuickLogic Corp
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Filing: 1990-09-05
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Granted: —
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Expires: 2010-09-05
Abstract
Abstract In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C, or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.
Inventors
- 👤 Ralph G. Whitten
- 👤 Richard L. Bechtel
- 👤 Mammen Thomas
- 👤 Hua-Thye Chua
- 👤 Andrew K. Chan
- 👤 John M. Birkner
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 23:36
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
127 words
A method of fabricating a programmable interconnect structure for an integrated circuit having a plurality of devices, comprising the steps of: fabricating a first conductor (33); fabricating an insulating layer (34) overlaying the first conductor; fabricating an opening through the insulating layer at a selected location and terminating the opening at a portion of the first conductor; depositing using plasma enhanced chemical vapor deposition a film (35) of amorphous silicon upon the insulating layer and in the opening; patterning the amorphous silicon film to form at the selected location an amorphous silicon feature substantially restricted to the opening and having a region contacting nd fully overlaying the first conductor portion; and fabricating a second conductor (36) of which a portion contacts and overlays the amorphous silicon region.
Claim 2
Independent Claim
127 words
A method of fabricating a programmable interconnect structure for an integrated circuit having a plurality of devices, comprising the steps of: fabricating a first conductor (33); fabricating an insulating layer (34) overlaying the first conductor; fabricating an opening through the insulating layer at a selected location and terminating the opening at a portion of the first conductor; depositing using plasma enhanced chemical vapor deposition a film (35) of amorphous silicon upon the insulating layer and in the opening; patterning the amorphous silicon film to form at the selected location an amorphous silicon feature substantially restricted to the opening and having a region contacting nd fully overlaying the first conductor portion; and fabricating a second conductor (36) of which a portion contacts and overlays the amorphous silicon region.
Claim 3
Dependent Claim
28 words
A method as claimed in claim 1 wherein plasma enhanced chemical vapor deposition proceeds at a temperature selected from the range 200 degrees C to 500 degrees C.
Claim 4
Dependent Claim
34 words
A method as claimed in claim 1 wherein the amorphous silicon depositing step comprises the step of establishing a reaction condition of argon at 225 degrees C, 340 degrees C or 380 degrees C.
Claim 5
Independent Claim
125 words
A method of fabricating a programmable interconnect structure for an integrated circuit having a plurality of devices, comprising the steps of: fabricating a first conductor (33); fabricating an insulating layer (34) overlaying the first conductor; fabricating an opening through the insulating layer at a selected location and terminating the opening at a portion of the first conductor; depositing using reactive sputter deposition a film (35) of amorphous silicon upon the insulating layer and in the opening; patterning the amorphous silicon film to form at the selected location an amorphous silicon feature substantially restricted to the opening and having a region contacting and fully overlaying the first conductor portion; and fabricating a second conductor (36) of which a portion contacts and overlays the amorphous silicon region.
Claim 6
Independent Claim
125 words
A method of fabricating a programmable interconnect structure for an integrated circuit having a plurality of devices, comprising the steps of: fabricating a first conductor (33); fabricating an insulating layer (34) overlaying the first conductor; fabricating an opening through the insulating layer at a selected location and terminating the opening at a portion of the first conductor; depositing using reactive sputter deposition a film (35) of amorphous silicon upon the insulating layer and in the opening; patterning the amorphous silicon film to form at the selected location an amorphous silicon feature substantially restricted to the opening and having a region contacting and fully overlaying the first conductor portion; and fabricating a second conductor (36) of which a portion contacts and overlays the amorphous silicon region.
Claim 7
Dependent Claim
32 words
A method as claimed in claim 1 or 4 wherein the depositing step comprises depositing the amorphous silicon film in a reactive gas atmosphere comprising argon, oxygen, hydrogen, nitrogen, fluorine, or chlorine.
Claim 8
Dependent Claim
28 words
A method as claimed in claim 1 or 4 comprising the step of ion implanting a dopant in the amorphous silicon film following the amorphous silicon depositing step.
Claim 9
Dependent Claim
18 words
A method as claimed in claim 6 wherein the dopant comprises argon, oxygen, hydrogen, nitrogen, fluorine, or chlorine.
Claim 10
Independent Claim
28 words
A method as claimed in any preceding claim wherein the first conductor fabricating step comprises the step of forming a refractory metal surface on the first conductor portion.
Claim 11
Independent Claim
28 words
A method as claimed in any preceding claim wherein the second conductor fabricating step comprises the step of forming a refractory metal surface on the second conductor portion.
Claim 12
Independent Claim
190 words
A method of fabricating a field programmable gate array, comprising the steps of: forming logic circuits for performing logic functions; forming I/O circuits for performing I/O functions; forming a first level of conductive routing channels (122,124) connected to select input and output terminals of the logic and I/O circuits; forming an insulating layer (34;132) overlaying the first level routing channels; forming openings through the insulating layer at selected locations and terminating the openings upon selected channels of the first level routing channels; blanket depositing using plasma enhanced chemical vapor deposition a film (35;142) of amorphous silicon upon the insulating layer, wherein the film is within the openings and contacts and fully overlays the first level channels at the select locations; patterning the amorphous silicon film to form at the selected locations respective amorphous silicon film areas substantially restricted to the openings; and forming a second level of conductive routing channels (144,146), the second level channels being connected to select input and output terminals of the logic and I/O circuits, and being transverse to the first level channels and in contact with and overlaying the film areas at the selected locations.
Claim 13
Independent Claim
190 words
A method of fabricating a field programmable gate array, comprising the steps of: forming logic circuits for performing logic functions; forming I/O circuits for performing I/O functions; forming a first level of conductive routing channels (122,124) connected to select input and output terminals of the logic and I/O circuits; forming an insulating layer (34;132) overlaying the first level routing channels; forming openings through the insulating layer at selected locations and terminating the openings upon selected channels of the first level routing channels; blanket depositing using plasma enhanced chemical vapor deposition a film (35;142) of amorphous silicon upon the insulating layer, wherein the film is within the openings and contacts and fully overlays the first level channels at the select locations; patterning the amorphous silicon film to form at the selected locations respective amorphous silicon film areas substantially restricted to the openings; and forming a second level of conductive routing channels (144,146), the second level channels being connected to select input and output terminals of the logic and I/O circuits, and being transverse to the first level channels and in contact with and overlaying the film areas at the selected locations.
Claim 14
Independent Claim
187 words
A method of fabricating a field programmable gate array, comprising the steps of: forming logic circuits for performing logic functions; forming I/O circuits for performing I/O functions; forming a first level of conductive routing channels (122,124) connected to select input and output terminals of the logic and I/O circuits; forming an insulating layer (34;132) overlaying the first level routing channels; forming openings through the insulating layer at selected locations and terminating the openings upon selected channels of the first level routing channels; blanket depositing using reactive sputter deposition a film (35;142) of amorphous silicon upon the insulating layer, wherein the film is within the openings and contacts and fully overlays the first level channels at the select locations; patterning the amorphous silicon film to form at the selected locations respective amorphous silicon film areas substantially restricted to the openings; and forming a second level of conductive routing channels, the second level channels being connected to select input and output terminals of the logic and I/O circuits, and being transverse to the first level channels and in contact with and overlaying the film areas at the selected locations.
Claim 15
Independent Claim
187 words
A method of fabricating a field programmable gate array, comprising the steps of: forming logic circuits for performing logic functions; forming I/O circuits for performing I/O functions; forming a first level of conductive routing channels (122,124) connected to select input and output terminals of the logic and I/O circuits; forming an insulating layer (34;132) overlaying the first level routing channels; forming openings through the insulating layer at selected locations and terminating the openings upon selected channels of the first level routing channels; blanket depositing using reactive sputter deposition a film (35;142) of amorphous silicon upon the insulating layer, wherein the film is within the openings and contacts and fully overlays the first level channels at the select locations; patterning the amorphous silicon film to form at the selected locations respective amorphous silicon film areas substantially restricted to the openings; and forming a second level of conductive routing channels, the second level channels being connected to select input and output terminals of the logic and I/O circuits, and being transverse to the first level channels and in contact with and overlaying the film areas at the selected locations.
Claim 16
Dependent Claim
133 words
A method as claimed in claim 10 or 11 wherein: the first level forming step comprises the step of forming selected ones of the first level channels in a plurality of discrete segments; the opening forming step comprises the step of forming openings through the insulating layer at selected locations proximate the opposing ends of the discrete segments, and terminating the openings upon the discrete segments; the patterning step comprises the step of patterning the amorphous silicon film to form, with respect to each pair of openings to adjacent channel segments, at least one amorphous silicon film area; and the second level forming step comprises the step of forming, with respect to each pair of openings to adjacent channel segments, a conductive segment in contact with and overlaying the film area associated therewith.
Claim 17
Independent Claim
152 words
A method of fabricating a programmable interconnect structure for an integrated circuit having a plurality of devices, comprising the steps of: fabricating a first conductor (33); fabricating an insulating layer (34) overlaying the first conductor; fabricating an opening through the insulating layer at a selected location and terminating the opening at a portion of said first conductor; depositing a first film (44;64) of amorphous or polycrystalline silicon upon the insulating layer and in the opening; forming a dielectric layer (45;65) on the first film; depositing a second film (46;66) of amorphous or polycrystalline silicon upon the dielectric layer; patterning the first and second films and the dielectric layer to form at the selected location an anti fuse feature substantially restricted to the opening and having a region contacting and fully overlaying the first conductor portion; and fabricating a second conductor (36) of which a portion contacts and overlays the antifuse feature region.
Claim 18
Independent Claim
152 words
A method of fabricating a programmable interconnect structure for an integrated circuit having a plurality of devices, comprising the steps of: fabricating a first conductor (33); fabricating an insulating layer (34) overlaying the first conductor; fabricating an opening through the insulating layer at a selected location and terminating the opening at a portion of said first conductor; depositing a first film (44;64) of amorphous or polycrystalline silicon upon the insulating layer and in the opening; forming a dielectric layer (45;65) on the first film; depositing a second film (46;66) of amorphous or polycrystalline silicon upon the dielectric layer; patterning the first and second films and the dielectric layer to form at the selected location an anti fuse feature substantially restricted to the opening and having a region contacting and fully overlaying the first conductor portion; and fabricating a second conductor (36) of which a portion contacts and overlays the antifuse feature region.
Claim 19
Dependent Claim
29 words
A method as claimed in claim 13 wherein the dielectric layer forming step comprises th step of growing a thermal oxide on the first film with rapid thermal anneal.
Claim 20
Dependent Claim
25 words
A method as claimed in claim 13 wherein the dielectric layer forming step comprises the step of exposing the first film to an oxidizing agent.
Claim 21
Dependent Claim
18 words
A method as claimed in claim 13, 14 or 15 comprising the step of doping the first film
Claim 22
Dependent Claim
19 words
A method as claimed in claim 13, 14, 15 or 16 comprising the step of doping the second film.
Claim 23
Independent Claim
136 words
A method of fabricating a programmable interconnect structure for an integrated circuit having a plurality of devices, comprising the steps of: fabricating a first conductor (33); fabricating an insulating layer (34) overlaying the first conductor; fabricating an opening through the insulating layer at a selected location and terminating the opening at a portion of the first conductor; depositing a film (55) of amorphous silicon upon the insulating layer and in the opening; forming a layer (56) of a conductive, highly diffusible material on the film; patterning the film and the diffusible layer to form at the selected location an antifuse feature substantially restricted to the opening, the feature having a region contacting and fully overlaying the first conductor portion; and fabricating a second conductor (36) of which a portion contacts and overlays the antifuse feature region.
Claim 24
Independent Claim
136 words
A method of fabricating a programmable interconnect structure for an integrated circuit having a plurality of devices, comprising the steps of: fabricating a first conductor (33); fabricating an insulating layer (34) overlaying the first conductor; fabricating an opening through the insulating layer at a selected location and terminating the opening at a portion of the first conductor; depositing a film (55) of amorphous silicon upon the insulating layer and in the opening; forming a layer (56) of a conductive, highly diffusible material on the film; patterning the film and the diffusible layer to form at the selected location an antifuse feature substantially restricted to the opening, the feature having a region contacting and fully overlaying the first conductor portion; and fabricating a second conductor (36) of which a portion contacts and overlays the antifuse feature region.
Claim 25
Independent Claim
126 words
A method of fabricating a programmable interconnect structure for an integrated circuit having a plurality of devices, comprising the steps of: fabricating a first conductor; fabricating an insulating layer overlaying the first conductor; fabricating an opening through the insulating layer at a selected location and terminating the opening at a portion of said first conductor; forming a layer of a conductive, highly diffusible material in the opening; depositing a film of amorphous silicon upon the diffusible layer; patterning the film and the diffusible layer to form at the selected location an antifuse feature substantially restricted to the opening and having a region contacting and fully overlaying the first conductor portion; and fabricating a second conductor of which a portion contacts and overlays the antifuse feature region.
Claim 26
Independent Claim
126 words
A method of fabricating a programmable interconnect structure for an integrated circuit having a plurality of devices, comprising the steps of: fabricating a first conductor; fabricating an insulating layer overlaying the first conductor; fabricating an opening through the insulating layer at a selected location and terminating the opening at a portion of said first conductor; forming a layer of a conductive, highly diffusible material in the opening; depositing a film of amorphous silicon upon the diffusible layer; patterning the film and the diffusible layer to form at the selected location an antifuse feature substantially restricted to the opening and having a region contacting and fully overlaying the first conductor portion; and fabricating a second conductor of which a portion contacts and overlays the antifuse feature region.
References Cited (Backward Citations)
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