Abstract A wafer-scale integrated circuit comprises a few hundred modules 10 which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs XINN, XINE, XINS, XINW from neighbouring modules and outputs thereto XOUTN, XOUTE, XOUTS, XOUTW, only one of which is enabled by one of four selection signals SELN, SELE, SELS, SELW acting both on transmit path logic 20 and on receive path logic 21 in a return path. A RAM unit 23 can be enabled by WRITE to write a block of data sent to RID via the transmit path and can be enabled to READ to read a block of data to ROD for return along the return path. The provision of SELN, etc READ and WRITE is effected by configuration logic 22 which includes a shift register and is responsive to a command mode signal CMND, on a line which runs to all modules in parallel.
A wafer-scale integrated circuit memory system including a plurality of circuit modules on a wafer, each module including a memory unit addressed by a free-running counter, an outward data path whereby data may be sent through the module to another module, an inbound data path whereby data may be sent back through the module from another module, configuration logic for selecting which of a set of neighbouring modules is the recipient of data sent on the outbound data path and is the source of data sent back on the inbound data path, and control means operable to select between a plurality of mutually exclusive states, namely a set of first states in one-to-one correspondence with the said neighbouring modules for causing the configuration logic to select a neighbouring module, a read state in which a data output of the memory unit is connected to the inbound data path and a write state in which a data input of the memory unit is connected to the outbound data path.
Claim 2
Dependent Claim
168 words
A wafer-scale integrated circuit memory system including a plurality of circuit modules on a wafer, each module including a memory unit addressed by a free-running counter, an outward data path whereby data may be sent through the module to another module, an inbound data path whereby data may be sent back through the module from another module, configuration logic for selecting which of a set of neighbouring modules is the recipient of data sent on the outbound data path and is the source of data sent back on the inbound data path, and control means operable to select between a plurality of mutually exclusive states, namely a set of first states in one-to-one correspondence with the said neighbouring modules for causing the configuration logic to select a neighbouring module, a read state in which a data output of the memory unit is connected to the inbound data path and a write state in which a data input of the memory unit is connected to the outbound data path.
Claim 3
Dependent Claim
23 words
A memory system according to claim 19, wherein the control means comprise a shift register with stages corresponding to the said states respectively.
Claim 4
Dependent Claim
82 words
A memory system according to claim 20, wherein the control means is responsive to a command signal distributed on a global command line to all modules to commence clocking a token bit down the shift register of a module in which the token bit is present on the outbound line when the command signal goes from a datum level to an active level and to cease clocking the token bit down the shift register whenthe command signal resets to the datum level.
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