Patent EP0416669A2 successfully refreshed from Google Patents.
EP0416669A2
Expired / Lapsed
EP
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Logic compiler for design of circuit models
Assignee: LSI Corp
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Filing: 1990-07-27
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Granted: —
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Expires: 2010-07-27
Abstract
Abstract A logic compiler wherein verification of a generated circuit model is performed automatically by comparing the operation of the circuit model with that of a corresponding mathematical behavior model. A novel user interface and circuit model generation means enables the user to obtain, in real time, performance specifications on the circuit selected by the user as well as incurring other benefits.
Inventors
- 👤 Jeffrey A. Werner
- 👤 Daniel R. Watkins
- 👤 Jimmy S. Wong
- 👤 Yen C. Chang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 12:30
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
163 words
A logic compiler for controlling a digital processor to generate a circuit model comprising: menu display means for controlling said processor to generate a series of displays in menu format; circuit model generation means for controlling said processor to generate a circuit model representative of a circuit selected by said user in response to input requests displayed in said series of displays; behavior model generation means for controlling said processor to generate a mathematical model corresponding to said circuit selected by said user; pattern file generating means for controlling said processor to generate a test pattern for input into a circuit model and corresponding behavior model; simulation means for controlling said processor to operate a circuit model and a behavior model upon a generated pattern file and store outputs from said circuit model and behavior model; and comparison means for controlling said processor to compare said outputs from said circuit model and said behavior model and identify corresponding outputs which are not identical.
Claim 2
Dependent Claim
163 words
A logic compiler for controlling a digital processor to generate a circuit model comprising: menu display means for controlling said processor to generate a series of displays in menu format; circuit model generation means for controlling said processor to generate a circuit model representative of a circuit selected by said user in response to input requests displayed in said series of displays; behavior model generation means for controlling said processor to generate a mathematical model corresponding to said circuit selected by said user; pattern file generating means for controlling said processor to generate a test pattern for input into a circuit model and corresponding behavior model; simulation means for controlling said processor to operate a circuit model and a behavior model upon a generated pattern file and store outputs from said circuit model and behavior model; and comparison means for controlling said processor to compare said outputs from said circuit model and said behavior model and identify corresponding outputs which are not identical.
Claim 3
Dependent Claim
48 words
The logic compiler of Claim 3 wherein said menu display means is for controlling said processor to generate a series of displays in menu format where a next display is dependent upon an input by a user in response to an input request displayed in a current display.
Claim 4
Dependent Claim
135 words
A digital processor for generating a circuit model comprising: menu display means for generating a series of displays in menu format; circuit model generation means for generating a circuit model representative of a circuit selected by said user in response to input requests displayed in said series of displays; behavior model generation means for generating a mathematical model corresponding to said specific circuit selected by said user; pattern file generating means for generating a test pattern for input into a circuit model and corresponding behavior model; simulation means for operating a circuit model and a behavior model upon a generated pattern file and storing outputs from said circuit model and behavior model; and comparison means for comparing said outputs from said circuit model and said behavior model and identifying corresponding outputs which are not identical.
Claim 5
Dependent Claim
135 words
A digital processor for generating a circuit model comprising: menu display means for generating a series of displays in menu format; circuit model generation means for generating a circuit model representative of a circuit selected by said user in response to input requests displayed in said series of displays; behavior model generation means for generating a mathematical model corresponding to said specific circuit selected by said user; pattern file generating means for generating a test pattern for input into a circuit model and corresponding behavior model; simulation means for operating a circuit model and a behavior model upon a generated pattern file and storing outputs from said circuit model and behavior model; and comparison means for comparing said outputs from said circuit model and said behavior model and identifying corresponding outputs which are not identical.
Claim 6
Dependent Claim
39 words
The digital processor of Claim 1 wherein said menu display means generates a series of displays where a next display is dependent upon an input by a user in response to an input request displayed in a current display.
Claim 7
Independent Claim
139 words
A method of verifying software in a logic compiler using a digital processor comprising the steps of: generating a circuit model capable of being created by said logic compiler; generating a behavior model corresponding to said circuit model; generating a pattern file consisting of one or more test vectors for application to said circuit model and said behavior model; applying each of said test vectors to said circuit model and said behavior model and obtaining an output of said circuit model and said behavior model associated with each of said test vectors; comparing outputs of said circuit model with outputs of said behavior model and identifying outputs of said circuit model and corresponding behavior model which are not identical to each other; and repeating the above steps for each circuit model capable of being generated by said logic compiler.
Claim 8
Independent Claim
139 words
A method of verifying software in a logic compiler using a digital processor comprising the steps of: generating a circuit model capable of being created by said logic compiler; generating a behavior model corresponding to said circuit model; generating a pattern file consisting of one or more test vectors for application to said circuit model and said behavior model; applying each of said test vectors to said circuit model and said behavior model and obtaining an output of said circuit model and said behavior model associated with each of said test vectors; comparing outputs of said circuit model with outputs of said behavior model and identifying outputs of said circuit model and corresponding behavior model which are not identical to each other; and repeating the above steps for each circuit model capable of being generated by said logic compiler.
Claim 9
Dependent Claim
30 words
The method of Claim 5 further comprising the step of determining loading of logic gates constituting said circuit model to identify gate delays which are longer than a predetermined criteria.
Claim 10
Independent Claim
85 words
A method of generating circuit models comprising the steps of: generating displays which include input requests directed to a user, wherein an input by the user determines a next display; and creating a circuit model of a selected circuit based on said input by said user using building blocks to create said circuit model, wherein said displays and input requests are presented to said user in an order which enables said circuit model to be modified by the addition of features selected by the user.
Claim 11
Independent Claim
85 words
A method of generating circuit models comprising the steps of: generating displays which include input requests directed to a user, wherein an input by the user determines a next display; and creating a circuit model of a selected circuit based on said input by said user using building blocks to create said circuit model, wherein said displays and input requests are presented to said user in an order which enables said circuit model to be modified by the addition of features selected by the user.
Claim 12
Dependent Claim
27 words
The method of Claim 7 wherein said building blocks are selected from the group consisting of transistors, logic gates, functional circuits, and register translation language level circuits
Claim 13
Independent Claim
58 words
A method of generating performance characteristics of a circuit model generated by a logic compiler using a digital processor comprising: generating a circuit model corresponding to a user's selected circuit; estimating a total delay between one or more input ports and one or more output ports of said circuit model; and displaying the resulting delay to said user.
Claim 14
Independent Claim
58 words
A method of generating performance characteristics of a circuit model generated by a logic compiler using a digital processor comprising: generating a circuit model corresponding to a user's selected circuit; estimating a total delay between one or more input ports and one or more output ports of said circuit model; and displaying the resulting delay to said user.
Claim 15
Dependent Claim
36 words
The method of Claim 9 further comprising the step of determining the number of logic gates used in said circuit model and area used and displaying the number of gates and area used to said user.
Claim 16
Independent Claim
113 words
A method of verifying the operation of a circuit model generated by a logic compiler using a digital processor, said circuit model being selected by a user, said method comprising the steps of: generating a behavior model corresponding to said circuit model; applying one or more test vectors to said circuit model and said behavior model and obtaining an output of said circuit model and said behavior model associated with each of said test vectors; comparing outputs of said circuit model with outputs of said behavior model and identifying outputs of said circuit model and corresponding behavior model which are not identical to each other; and displaying the resulting outputs to said user.
Claim 17
Independent Claim
113 words
A method of verifying the operation of a circuit model generated by a logic compiler using a digital processor, said circuit model being selected by a user, said method comprising the steps of: generating a behavior model corresponding to said circuit model; applying one or more test vectors to said circuit model and said behavior model and obtaining an output of said circuit model and said behavior model associated with each of said test vectors; comparing outputs of said circuit model with outputs of said behavior model and identifying outputs of said circuit model and corresponding behavior model which are not identical to each other; and displaying the resulting outputs to said user.
References Cited (Backward Citations)
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