E2PROM with a floating gate formed in a semiconductor substrate and method of fabricating the same

Claim 1

A semiconductor memory device having a stacked structure of a floating gate, a control gate and an erase gate, for storing data based on whether or not electrons are accumulated in said floating gate and erasing stored data using said erase gate, characterized by comprising a semiconductor substrate (21) of a first conductivity type, a field insulating film (22) selec­tively formed on a major surface of said semiconductor substrate (21), a source region (23) and a drain region (24) of a second conductivity type, formed in an element region on a major surface region of said semiconductor substrate (21), separated from each other at a predeter­mined interval, a groove (25) formed in said major sur­face of said semiconductor substrate (21) between said source region (23) and said drain region (24), a first insulating film (26) formed on a surface of said semi­conductor substrate (21) at bottom and side wall por­tions of said groove (25), a floating gate (27) formed in said groove (25), a thin second insulating film (28-1) formed on part of a surface of said floating gate (27), an erase gate (29) formed on said second insulat­ing film (28-1) and part of said field insulating film (22), a third insulating film (28-2) formed on a surface of said erase gate (29) and the other part of said floating gate (27), and a control gate (30) formed on said third insulating film (28-2).

Claim 10

A method of fabricating a semiconductor memory device having a stacked structure of a floating gate, a control gate and an erase gate, for storing data based on whether or not electrons are accumulated in said floating gate and erasing stored data using said erase gate, characterized by comprising the steps of selec­tively forming a field insulating film (22) for element isolation on a major surface of a semiconductor subst­rate (21), forming a groove (25) in an element region on said major surface of said semiconductor substrate (21), forming a first insulating film (26) on bottom and side wall portions of said groove (25), forming a floating gate (27) in said groove (25), forming a thin second insulating film (28-1) on a surface of said floating gate (27), forming an erase gate (29) on said second insulating film (28-1) on part of said floating gate (27) and part of said field insulating film (22), form­ing a third insulating film (28-2) on a surface of said erase gate (29) and the other part of said floating gate (27), forming a control gate (30) on said third insulat­ing film (28-2), and forming a source region (23) and a drain region (24) in a major surface region of said sem­iconductor substrate (21) on both sides of said groove (25).

Claim 11

A method of fabricating a semiconductor memory device having a stacked structure of a floating gate, a control gate and an erase gate, for storing data based on whether or not electrons are accumulated in said floating gate and erasing stored data using said erase gate, characterized by comprising the steps of selec­tively forming a field insulating film (22) for element isolation on a major surface of a semiconductor subst­rate (21), forming a groove (25) in an element region on said major surface of said semiconductor substrate (21), forming a first insulating film (26) on bottom and side wall portions of said groove (25), forming a floating gate (27) in said groove (25), forming a thin second insulating film (28-1) on a surface of said floating gate (27), forming an erase gate (29) on said second insulating film (28-1) on part of said floating gate (27) and part of said field insulating film (22), form­ing a third insulating film (28-2) on a surface of said erase gate (29) and the other part of said floating gate (27), forming a control gate (30) on said third insulat­ing film (28-2), and forming a source region (23) and a drain region (24) in a major surface region of said sem­iconductor substrate (21) on both sides of said groove (25).