Patent EP0416331A2 successfully refreshed from Google Patents.
EP0416331A2
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Line computer
Assignee: Yokogawa Electric Corp
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Filing: 1990-08-14
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Granted: —
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Expires: 2010-08-14
Abstract
Abstract In a line computer used for controlling a manufacturing line control system, in which a high speed CPU and low speed I/O devices are used, optimum bus timing for signal transmission can be generated, which has enough time margin to adjust speed difference between the high speed CPU and the low speed I/O devices. Further, function of a calendar clock is improved so that the accurate time can be generated. Furthermore, display memory in a CRT displaying controller is used effectively so that the number of memory elements can be reduced. Still furthermore, connection system between the CPU board and I/O boards or floppy disk drives is improved so that abnormality of the peripheral equipments does not expand to the CPU board. Still furthermore, in this invention, compiler type language such as C language can coexist with interpreter type language such as BASIC language.
Inventors
- 👤 Hirokazu Tairaku
- 👤 Kenichi Inoue
- 👤 Chiaki Ito
- 👤 Kenji Takimoto
- 👤 Shigetoshi Tanido
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 21:21
CPC Classifications
G; G06; G06F; G06F17/00; G06F9/00; G06F9/06; G06F9/44; G06F9/445; G06F9/44521; G05; G05B; G05B19/00; G05B19/02; G05B19/18; G05B19/414; G05B19/4142; G05B19/418; G05B19/4181; G06F9/455; G06F9/45504; G06F9/45508; G05B2219/00; G05B2219/30; G05B2219/33; G05B2219/33085; G05B2219/33087; G05B2219/33162; G05B2219/33164; G05B2219/33169; G05B2219/33226; G05B2219/33323; G05B2219/34; G05B2219/34356; G05B2219/34421; G05B2219/34453; G05B2219/35; G05B2219/35547; G05B2219/36; G05B2219/36031; G05B2219/36112; G05B2219/36371; Y; Y02; Y02P; Y02P90/00; Y02P90/02
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
401 words
A line computer, comprising: a main processor controlling each element which comprises the line computer; a first bus connected to said main processor; a main memory connected to said first bus, and accessed by said main processor; a DMA controller connected to said first bus, which executes direct memory access with said main memory and a SCSI controller or floppy disk controller; a VME-bus controller connected to said first bus, which controls various I/O boards; a second bus having a smaller bit number than that of said first bus; a timing control circuit connected between said first bus and said second bus, which comprises a buffer and a control circuit, wherein: said buffer latches data on said first bus or said second bus; and said control circuit functions to delay an address strobe signal and a data strobe signal asserted by said main processor when a read signal is applied from said main processor, said control circuit transmitting a chip select signal for prohibiting transmission before said address strobe signal and said data strobe signal are negated, said control circuit instructing to store the read data in said buffer and generating a timing signal by which the stored data is transmitted to said first bus, said control circuit functioning to delay the address strobe signal and the data strobe signal asserted by said main processor when a write signal is applied from said main processor, said control circuit instructing to store the write data in said buffer and generating a timing signal by which the stored data is transmitted to said second bus, and afterwards said control circuit generating said chip select signal; a CRT displaying controller connected to said second bus, which has a graphic display controller to control graphic display on a CRT display apparatus and a character display controller to control character display; a communication processing portion connected to said second bus, which executes communication processing with other line computers; a third bus having a smaller bit number than that of said first bus; a slave processor connected to said third bus; a calendar clock which transmits clock signal to said slave processor; a peripheral device control portion connected to said third bus, which controls a printer, serial signal communication and a keyboard; and a peripheral controller arranged between said first bus and said third bus, which adjusts operation timing of said main processor and said slave processor.
Claim 2
Dependent Claim
401 words
A line computer, comprising: a main processor controlling each element which comprises the line computer; a first bus connected to said main processor; a main memory connected to said first bus, and accessed by said main processor; a DMA controller connected to said first bus, which executes direct memory access with said main memory and a SCSI controller or floppy disk controller; a VME-bus controller connected to said first bus, which controls various I/O boards; a second bus having a smaller bit number than that of said first bus; a timing control circuit connected between said first bus and said second bus, which comprises a buffer and a control circuit, wherein: said buffer latches data on said first bus or said second bus; and said control circuit functions to delay an address strobe signal and a data strobe signal asserted by said main processor when a read signal is applied from said main processor, said control circuit transmitting a chip select signal for prohibiting transmission before said address strobe signal and said data strobe signal are negated, said control circuit instructing to store the read data in said buffer and generating a timing signal by which the stored data is transmitted to said first bus, said control circuit functioning to delay the address strobe signal and the data strobe signal asserted by said main processor when a write signal is applied from said main processor, said control circuit instructing to store the write data in said buffer and generating a timing signal by which the stored data is transmitted to said second bus, and afterwards said control circuit generating said chip select signal; a CRT displaying controller connected to said second bus, which has a graphic display controller to control graphic display on a CRT display apparatus and a character display controller to control character display; a communication processing portion connected to said second bus, which executes communication processing with other line computers; a third bus having a smaller bit number than that of said first bus; a slave processor connected to said third bus; a calendar clock which transmits clock signal to said slave processor; a peripheral device control portion connected to said third bus, which controls a printer, serial signal communication and a keyboard; and a peripheral controller arranged between said first bus and said third bus, which adjusts operation timing of said main processor and said slave processor.
Claim 3
Dependent Claim
192 words
The line computer of claim 1, wherein said calendar clock to generate a software timer interruption signal comprises: a divider which generates frequency divided clock by frequency-dividing the standard clock applied from an identical standard clock generating means; a first counting means counting said divided clock until the number which is larger by one clock than that equivalent to a fixed software timer interruption period, and generating an output as said software timer interruption signal; a second counting means counting said divided clock until the number which is smaller by one clock than that equivalent to said software timer interruption period, and generating an output as said software timer interruption period; setting means for setting a first setting value and a second setting value in such a way as (the clock number which coincides with multiple of the time equivalent to said software timer interruption period) = (the clock number counted by said first counting means)*(a first setting value) + (the clock number counted by said second counting means)*(a second setting value); and switching means for switching said first counting means and said second counting means in accordance with each counted value.
Claim 4
Dependent Claim
153 words
The line computer of claim 1, wherein: information storage area of a single memory element in said character display controller in said CRT displaying controller, is divided into a code area, an attribute area and a font area; character code, attribute data and font pattern are stored in said areas respectively; and reading operation in said code area, reading operation in attribute area, read/write access from said main processor to said memory, reading operation in said font area corresponding to the character code read out from said code area are executed sequentially and in time-sharing manner, or simultaneous reading operation both in said code area and said attribute area, read/write access from said main processor to said memory, reading operation in said font area corresponding to the character code read out from said code area are executed sequentially and in time-sharing manner, one display cycle being constituted by a set of these operation.
Claim 5
Dependent Claim
152 words
The line computer of claim 1, wherein: said VME-bus controller has multiple I/O boards connected to VME-bus; I/O board drivers are set on the main processor side corresponding to respective said I/O boards; a control circuit for generating a fail signal when abnormality is detected in said I/O board, is provided; abnormality detection means is provided, which generates diagnosis request in response to the fail signal on the main processor side; a self-diagnosis portion is provided in said I/O board driver, which makes said I/O board execute self-diagnosis operation in response to said diagnosis request and receives the result of the self-diagnosis from said I/O board; and board separating means is provided in said I/O board driver, which gives a separating signal to said control circuit when said diagnosis signal represents abnormality, so as to separate said I/O driver from said main processor side and turn said I/O driver to error state.
Claim 6
Dependent Claim
68 words
The line computer of claim 1, wherein: at least one or more floppy disk drives are connected to said floppy disk controller in a daisy chain manner; terminal resistors are provided in respective daisy chain receivers in said floppy disk drives; and buffers are provided, in parallel, in said daisy chain receivers in all floppy disk drives other than the floppy disk drive installed at the most rear.
Claim 7
Dependent Claim
179 words
In a method of installing compiler type language into interpreter type language, the improvement wherein: execution form program of said compiler type language is arranged at the rear of said interpreter type language program in the user area of the memory; the execution form program comprises: a) procedure for piling up various arguments in said interpreter type language program, in a stack; b) procedure for copying static variable data previously set in a data area to said execution form program, as an initial value, every time when said interpreter type language program is executed; c) procedure for changing branch destination address wherein relative address from top address in C library area to position dependent code address in said C library area, and relative address from the top address in said C library area to the branch destination address included in said position dependent code in said C library area are set in a table, said branch destination address being rewritten, when said interpreter type language is amended and then the top address in said C library area is changed.
Claim 8
Dependent Claim
179 words
In a method of installing compiler type language into interpreter type language, the improvement wherein: execution form program of said compiler type language is arranged at the rear of said interpreter type language program in the user area of the memory; the execution form program comprises: a) procedure for piling up various arguments in said interpreter type language program, in a stack; b) procedure for copying static variable data previously set in a data area to said execution form program, as an initial value, every time when said interpreter type language program is executed; c) procedure for changing branch destination address wherein relative address from top address in C library area to position dependent code address in said C library area, and relative address from the top address in said C library area to the branch destination address included in said position dependent code in said C library area are set in a table, said branch destination address being rewritten, when said interpreter type language is amended and then the top address in said C library area is changed.
References Cited (Backward Citations)
No citation records indexed.
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