Patent EP0415660A2 successfully refreshed from Google Patents.
EP0415660A2
Expired / Lapsed
EP
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FET having a high trap concentration interface layer and method of fabrication
Assignee: Motorola Solutions Inc
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Filing: 1990-08-24
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Granted: —
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Expires: 2010-08-24
Abstract
Abstract A FET (42) having a high trap concentration interface layer (46) and method of fabrication includes a semi-insulating gallium arsenide substrate (44) having a high trap concentration interface layer (46) formed therein. An non-intentionally doped buffer layer (48), also comprised of gallium arsenide, is then formed on the interface layer (46) and is followed by the formation of a doped aluminum gallium arsenide layer (50) thereon. A source (56), a gate (60) and a drain (58) are then formed on the FET layers. The FET (42) and method disclosed herein are especially applicable for low current (5-1000 microamp) operation of microwave low-noise FETs.
Inventors
- 👤 Herbert Goronkin
- 👤 Saied Nikoo Tehrani
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 03:48
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/50; H10D62/53
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
73 words
A FET (42) having a high trap concentration interface layer (46) comprising: a semi-insulating substrate (44); the invention being characterized by: a high trap concentration interface layer (46) formed in said substrate (44); a non-intentionally doped buffer layer (48) formed on said high trap concentration interface layer (46); a layer (50) formed on said buffer layer (48); and a source (56), a gate (60) and a drain (58) formed on the FET layers.
Claim 2
Dependent Claim
73 words
A FET (42) having a high trap concentration interface layer (46) comprising: a semi-insulating substrate (44); the invention being characterized by: a high trap concentration interface layer (46) formed in said substrate (44); a non-intentionally doped buffer layer (48) formed on said high trap concentration interface layer (46); a layer (50) formed on said buffer layer (48); and a source (56), a gate (60) and a drain (58) formed on the FET layers.
Claim 3
Dependent Claim
18 words
The FET (42) of claim 1 wherein the semi-insulating substrate (44) comprises a III-V compound semiconductor or silicon.
Claim 4
Dependent Claim
22 words
The FET (42) of claim 2 wherein the high trap concentration interface layer (46) and the buffer layer(48) comprise the same material.
Claim 5
Dependent Claim
22 words
The FET (42) of claim 3 wherein the high trap concentration interface layer (46) and the buffer layer (48) comprise gallium arsenide.
Claim 6
Dependent Claim
25 words
The FET (42) of claim 2 wherein the high trap concentration interface layer (46) is formed in the semi-insulating substrate (44) by implanting oxygen therein.
Claim 7
Dependent Claim
19 words
The FET (42) of claim 5 wherein the implanting of oxygen is done in either blanket or selective form.
Claim 8
Dependent Claim
25 words
The FET (42) of claim 2 wherein the high trap concentration interface layer (46) is formed in the semi-insulating substrate (44) by implanting boron therein.
Claim 9
Dependent Claim
19 words
The FET (42) of claim 7 wherein the implanting of boron is done in either blanket or selective form.
Claim 10
Independent Claim
95 words
A method of fabricating a FET (42) having a high trap concentration interface layer (46) comprising the steps of: providing a III-V compound or silicon semi-insulating substrate (44); the invention being characterized by: forming a high trap concentration interface layer (46) in said substrate (44) by implanting oxygen therein; forming an non-intentionally doped gallium arsenide buffer layer (48) on said high trap concentration interface layer (46); forming a doped aluminum gallium arsenide layer (50) on said buffer layer (48); and forming a source (56), a gate (60) and a drain (58) on the FET layers.
Claim 11
Independent Claim
95 words
A method of fabricating a FET (42) having a high trap concentration interface layer (46) comprising the steps of: providing a III-V compound or silicon semi-insulating substrate (44); the invention being characterized by: forming a high trap concentration interface layer (46) in said substrate (44) by implanting oxygen therein; forming an non-intentionally doped gallium arsenide buffer layer (48) on said high trap concentration interface layer (46); forming a doped aluminum gallium arsenide layer (50) on said buffer layer (48); and forming a source (56), a gate (60) and a drain (58) on the FET layers.
References Cited (Backward Citations)
No citation records indexed.
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