Semiconductor memory device having stacked capacitor and method of producing the same

Claim 2

A semiconductor memory device as claimed in claim 1, wherein the said side wall structure (22) includes a plurality of side wall portions each made of conductive material and formed alongside the stack.

Claim 3

A semiconductor memory device as claimed in claim 1 or 2, wherein the said side wall structure (22) has a rounded top surface which meets with an upper main face of an uppermost one (15₃) of the said further conductive layers (15₂, 15₃) at substantially the level of that upper main face.

Claim 4

A semiconductor memory device as claimed in claim 3, wherein the said uppermost one (15₃) of the said further conductive layers (15) is greater in thickness than the other further conductive layers (15₂).

Claim 5

A semiconductor memory device as claimed in any one of claims 1 to 4, wherein the said first conductive layer (15₁) occupies a generally rectangular area above the said substrate (1), and the said side wall structure (22) is formed alongside at least two mutually adjacent sides of the generally rectangular area.

Claim 6

A semiconductor memory device as claimed in any one of claims 1 to 4, wherein the said first conductive layer (15₁) occupies a generally rectangular area above the said substrate (1), and the said side wall structure (22) is formed alongside at least two mutually opposing sides of the generally rectangular area.

Claim 7

A semiconductor memory device as claimed in any one of claims 1 to 4, wherein the said first conductive layer (15₁) occupies a generally rectangular area above the said substrate (1), and the said side wall structure (22) is formed alongside all four sides of the generally rectangular area.

Claim 8

A semiconductor memory device as claimed in claim 7, wherein the or each further conductive layer (15₂, 15₃) extends from the side wall structure (22) as far as a central portion of the generally rectangular area but does not extend above that central portion of the generally rectangular area.

Claim 9

A semiconductor memory device as claimed in any one of claims 1 to 8, wherein there are provided a first interlayer insulator (26) covering the said second electrode structure (25) and having a contact opening above the other active region (5) of the said transfer transistor, a bit line (27) which is formed on the said first interlayer insulator (25), and a stacked connection structure formed in the said contact opening for electrically connecting the said bit line to the said other active region of the said transfer transistor, the said stacked conductor structure including a further stack of alternate conductive and spacing layers (15₁-15₃, 29₁-29₃) and also including a further side wall structure (22) formed alongside the said further stack so as to be connected physically to mutually-corresponding respective outer edge regions of the conductive layers of the said further stack, so that the said conductive layers (15₁-15₃) of the further stack are connected electrically together.

Claim 10

A semiconductor memory device as claimed in claim 9, further including a word line (4₂) formed, between the said source and drain regions (6₂; 5) of the transfer transistor, on a gate insulator film (3) of the said insulator layer (2, 3), and a second interlayer insulator (7) which covers the word line, the said first conductive layer (15₁) having a portion which overlaps the said word line.

Claim 11

A semiconductor memory device as claimed in claim 9 or 10, wherein the top surface of the said stacked connection structure is at approximately the same level as the upper main face of the uppermost further conductive layer (15₃) in the said first electrode structure.

Claim 12

A semiconductor memory device as claimed in claim 9, 10 or 11, wherein the said spacing layers (29₁-29₃) are made of a conductive material selected from a group including carbon.

Claim 14

A method as claimed in claim 13, wherein: the said insulator layer (2,3,7) is also formed with a further contact hole through which a part of the other active region (5) is exposed, the insulator layer (2,3,7) being provided by forming a gate insulator film (3) on the said substrate above the transfer transistor, forming a word line (4₂) on the gate insulator film (3) between the said source and drain regions (6₂,5), and forming a first interlayer insulator (7) over the word line (4₂), the contact hole of claim 13 and the said further contact hole each passing through the said first interlayer insulator (7) and the gate insulator film (3); and the alternate conductive and spacing layers (15 1,2,3 ; 29 1,2,3 ) are stacked on the said first interlayer insulator (7) and on the respective exposed parts of the two active regions (6₂,5), such that the lowermost of the stacked layers (15₁) also contacts the said exposed part of the said other active region (5) through the said further contact hole, and then the stacked layers (15 1,2,3 ; 29 1,2,3 ) are patterned to form the said stack of claim 13 and a further stack of the layers, separated from the stack of claim 13, above the said further contact hole; the method comprising the further steps of: forming a further side wall structure (22) made of conductive material alongside the said further stack so as to be connected physically to mutually-corresponding respective outer edge regions of the layers of the further stack, so that the said conductive layers (15) of the further stack together with the said further side wall structure (22) constitute a stacked connection structure; providing on the said second electrode structure a second interlayer insulator (26) formed with a contact opening through which an upper part of the said stacked connection structure is exposed; and forming conductive material (27) on the said second interlayer insulator and on the exposed upper part of the further stack, so that the conductive material, which serves as a bit line of the device, is connected electrically to the said other active region of the transfer transistor via the said stacked connection structure.

Claim 15

A method as claimed in claim 13 or 14, wherein the said spacing layers (29₁-29₃) are made of carbon.