Pipelined processor with variable instruction length

Claim 2

A data processing device for executing a variable length instruction, wherein said data processing device comprises: an instruction buffer memory (IB) having a plurality of rows, each of said rows storing a plurality of bit string units; a read pointer (5), for indicating one of said rows; an instruction decoder (9) supplied with said bit string units; a latch means (7), connected to said instruction buffer memory (IB), for storing bit string units read out in an immediately preceding step from one of said rows; and a select means (6), for selecting an output of said instruction buffer memory (IB) or an output of said latch means (7) to supply a beginning bit string unit of the instruction and subsequent bit string unit.

Claim 3

A data processing device as claimed in claim 1, wherein each of said rows in said instruction buffer memory (IB) is divided into a plurality of blocks (Ho-H 3 ).

Claim 4

A data processing device as claimed in claim 2, wherein each of said blocks (H o -H 3 ) includes a plurality of memory cells (a 1l ~ a mn ), said latch means (7) includes a plurality of latch circuits (70- 73), said select means (6) includes a plurality of select circuits (60-63), and each select circuit group (60-63) is controlled to output data selected from a combination data of the output of said instruction buffer memory (IB) and the output of said latch means (7).

Claim 5

A data processing device as claimed in claim 3, wherein each of said memory cells (a11-amn) in one of said rows is connected to a single word line (WL) through a single gate transistor and a single bit line (BL) for a reading out operation.

Claim 6

A data processing device according to any preceding claim, wherein the bit string units selected by said select means (6) are transferred through a transfer circuit (8) to said instruction decoder (9).

Claim 7

A data processing device as claimed in claim 5, wherein said transfer circuit (8) rotates a plurality of bit string units (E, F, C, D) constituting said instruction bit string for changing the order of said bit string units to an original order (C, D, E, F).

Claim 8

A data processing device according to any preceding claim, wherein said data processing device is used for a variable length instruction system using pipeline processing.

Claim 9

A data processing device comprising, a memory management unit (1), an instruction buffer memory (IB) connected to said memory management unit (1), and an instruction decoder (9), connected to said instruction buffer memory (IB), for decoding an instruction bit string transferred from said instruction buffer memory (IB), for discriminating an instruction length of said instruction contained in said instruction bit string, and for outputting an instruction length notification signal, wherein said instruction buffer memory (IB) comprises: a memory portion (N), for storing instruction bit strings; a latch circuit (7), for temporarily holding an instruction bit string transferred in an immediately preceding step; a validity control portion (3), for outputting a unit validity flag indicating whether each bit string unit constituting said instruction bit string transferred to said instruction decoder (9) is valid or not as an instruction; a read pointer control portion (4), for indicating a memory position in said memory portion (N) where said instruction bit strings transferred to said instruction decoder (9) has been stored; a read pointer (5), for indicating another memory position obtained by shifting by a unit length corresponding to the number of said unit validity flag, from the memory position indicated by said read pointer control portion (4); and a select circuit (6), for selecting a next instruction bit string sequentially continuing from a next instruction, between a first instruction bit string and a second instruction bit string, said first instruction bit string being previously read out from a plurality of memory cells (a i ~a mn ) in said memory portion (N) to a plurality of bit lines (BL) by a memory position indicated by said read pointer (5) being a start point, and said second instruction bit string being temporarily held in said latch circuit (7) by an instruction length notification signal output from said instruction decoder (9).

Claim 10

A data processing device comprising, a memory management unit (1), an instruction buffer memory (IB) connected to said memory management unit (1), and an instruction decoder (9), connected to said instruction buffer memory (IB), for decoding an instruction bit string transferred from said instruction buffer memory (IB), for discriminating an instruction length of said instruction contained in said instruction bit string, and for outputting an instruction length notification signal, wherein said instruction buffer memory (IB) comprises: a memory portion (N), for storing instruction bit strings; a latch circuit (7), for temporarily holding an instruction bit string transferred in an immediately preceding step; a validity control portion (3), for outputting a unit validity flag indicating whether each bit string unit constituting said instruction bit string transferred to said instruction decoder (9) is valid or not as an instruction; a read pointer control portion (4), for indicating a memory position in said memory portion (N) where said instruction bit strings transferred to said instruction decoder (9) has been stored; a read pointer (5), for indicating another memory position obtained by shifting by a unit length corresponding to the number of said unit validity flag, from the memory position indicated by said read pointer control portion (4); and a select circuit (6), for selecting a next instruction bit string sequentially continuing from a next instruction, between a first instruction bit string and a second instruction bit string, said first instruction bit string being previously read out from a plurality of memory cells (a i ~a mn ) in said memory portion (N) to a plurality of bit lines (BL) by a memory position indicated by said read pointer (5) being a start point, and said second instruction bit string being temporarily held in said latch circuit (7) by an instruction length notification signal output from said instruction decoder (9).

Claim 11

A data processing device as claimed in claim 8, wherein said instruction buffer memory (IB) is divided into a plurality of blocks (Ho-H 3 ) each constituted by a half word.

Claim 12

A data processing device as claimed in claim 9, wherein each of said blocks (H o -H 3 ) includes a plurality of memory cells (ai, ~a mn ), a latch circuit (70-73), and a select circuit (60-63), respectively.

Claim 13

A data processing device as claimed in claim 10, wherein each of said memory cells (a 1l ~ a mn ) in a row is connected to a single word line (WL) through a single gate transistor and a single bit line (BL) for a reading out operation.

Claim 14

A data processing device as claimed in claim 8, wherein an instruction bit string output from said instruction buffer memory (IB) is transferred through a transfer circuit (8) to said instruction decoder (9).

Claim 15

A data processing device as claimed in claim 12, wherein said transfer circuit (8) rotates a plurality of bit string units (E, F, C, D) constituting said instruction bit string for changing the order of said bit string units to an original order (C, D, E, F).

Claim 16

A data processing device as claimed in claim 8, wherein said data processing device is used for a variable length instruction system using pipeline processing.

Claim 17

A data processing device comprising: an instruction decoder (9) decoding an instruction bit string and discriminating an instruction length of said instruction contained in said instruction bit string, and for outputting an instruction length notification signal; and an instruction buffer memory (IB), connected to said instruction decoder (9), for transferring an instruction bit string to said instruction decoder (9), including: a memory means (N), for storing instruction bit strings; a latch means (7), for temporarily holding an instruction bit string transferred in an immediately preceding step; a validity control means (3), for outputting a unit validity flag indicating whether each bit string units constituting said instruction bit string transferred to said instruction decoder (9) is valid or not as an instruction; a read pointer control means (4), for indicating a memory position in said memory means (N) where said instruction bit strings transferred to said instruction decoder (9) has been stored; a read pointer (5) indicating another memory position obtained by shifting by a unit length corresponding to the number of said unit validity flag, from the memory position indicated by said read pointer control means (4); and a select means (6) for selecting a next instruction bit string sequentially continuing from a next instruction, between a first instruction bit string and a second instruction bit string, said first instruction bit string being previously read out from a plurality of memory cells (a 1l ~ a mn ) in said memory means (N) to a plurality of bit lines (BL) by a memory position indicated by said read pointer (5) being a start point, and said second instruction bit string being temporarily held in said latch means (7) by an instruction length notification signal output from said instruction decoder (9).

Claim 18

A data processing device comprising: an instruction decoder (9) decoding an instruction bit string and discriminating an instruction length of said instruction contained in said instruction bit string, and for outputting an instruction length notification signal; and an instruction buffer memory (IB), connected to said instruction decoder (9), for transferring an instruction bit string to said instruction decoder (9), including: a memory means (N), for storing instruction bit strings; a latch means (7), for temporarily holding an instruction bit string transferred in an immediately preceding step; a validity control means (3), for outputting a unit validity flag indicating whether each bit string units constituting said instruction bit string transferred to said instruction decoder (9) is valid or not as an instruction; a read pointer control means (4), for indicating a memory position in said memory means (N) where said instruction bit strings transferred to said instruction decoder (9) has been stored; a read pointer (5) indicating another memory position obtained by shifting by a unit length corresponding to the number of said unit validity flag, from the memory position indicated by said read pointer control means (4); and a select means (6) for selecting a next instruction bit string sequentially continuing from a next instruction, between a first instruction bit string and a second instruction bit string, said first instruction bit string being previously read out from a plurality of memory cells (a 1l ~ a mn ) in said memory means (N) to a plurality of bit lines (BL) by a memory position indicated by said read pointer (5) being a start point, and said second instruction bit string being temporarily held in said latch means (7) by an instruction length notification signal output from said instruction decoder (9).

Claim 19

A monolithic microprocessor formed in a single semiconductor body, comprising an instruction control unit (41) for controlling fetching, decoding, and executing of instructions, an instruction execution unit (42) for calculating an operand address and executing an operand operation, a memory management unit (43, 1), and a bus control unit (44) for transferring data among an external I/O, an external memory, and said data processing device through the chip bus, wherein said instruction control unit (41) comprises: an instruction decoder (412, 9), for decoding an instruction bit string, for discriminating an instruction length of said instruction contained in said instruction bit string, and for outputting an instruction length notification signal; and a data processing device according to any of claims 1 to 7.

Claim 20

A data processing method for supplying a variable length instruction from an instruction buffer memory (IB) to an instruction decoder (9), wherein said data processing method comprises: temporarily holding a first instruction bit string read out in an immediately preceding step from said instruction buffer memory (IB); reading out a second instruction bit string from said instruction buffer memory (IB) at a memory position indicated by a read pointer (5); and selecting instruction bit strings from among the first and second instruction bit strings.

Claim 21

A data processing method for supplying a variable length instruction from an instruction buffer memory (IB) to an instruction decoder (9), wherein said data processing method comprises: temporarily holding a first instruction bit string read out in an immediately preceding step from said instruction buffer memory (IB); reading out a second instruction bit string from said instruction buffer memory (IB) at a memory position indicated by a read pointer (5); and selecting instruction bit strings from among the first and second instruction bit strings.