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EP0413347A2
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Semiconductor nonvolatile memory device
Assignee: Hitachi Ltd
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Filing: 1990-08-17
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Granted: —
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Expires: 2010-08-17
Abstract
Abstract An electrically erasable semiconductor memory device is disclosed which makes it possible to detect the presence of the memory cell whose threshold voltage becomes negative after erase operation. The information stored in the memory cells are read while all gates of the memory cells are kept on the voltage to make them nonselective in order to easily and quickly detect the memory cell whose threshold voltage is negative.
Inventors
- 👤 Koichi Seki
- 👤 Takeshi Wada
- 👤 Tadashi Muto
- 👤 Kazuo Izawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 21:23
CPC Classifications
G; G11; G11C; G11C17/00; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/344; G11C16/345; G11C16/26; G11C29/00; G11C29/04; G11C29/50; G11C29/50004; G06; G06F; G06F2201/00; G06F2201/81; G11C16/04
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
96 words
A semiconductor memory device comprising: a memory array comprising a plurality of electrically erasable nonvolatile memory elements arranged in a matrix, each memory element being selected by a single word line and a single data line, wherein a gate of said memory element is connected to said word line and a drain of said memory element is connected to said data line; a first circuit reading out information stored in said memory element; and a second circuit grounding the gates of all said memory elements of said memory array during read operation of said memory device.
Claim 2
Dependent Claim
96 words
A semiconductor memory device comprising: a memory array comprising a plurality of electrically erasable nonvolatile memory elements arranged in a matrix, each memory element being selected by a single word line and a single data line, wherein a gate of said memory element is connected to said word line and a drain of said memory element is connected to said data line; a first circuit reading out information stored in said memory element; and a second circuit grounding the gates of all said memory elements of said memory array during read operation of said memory device.
Claim 3
Dependent Claim
21 words
A semiconductor memory device according to claim 1, wherein said second circuit grounds said gates in response to an external signal.
Claim 4
Dependent Claim
20 words
A semiconductor memory device according to claim 2, wherein said external signal is a signal which specifies a depletion test.
Claim 5
Dependent Claim
122 words
A semiconductor memory device comprising: a memory array comprising a plurality of electrically erasable nonvolatile memory elements arranged in a matrix and a plurality of word lines, each memory element being selected by one of said word lines and a single data line, gate of said memory element is connected to said word line and drain of said memory element is connected to said data line, sensing circuit reading out information stored in said memory element; and an address decoder specifying one word line in response to an address signal in a first mode, and for grounding all word lines regardless of said address signal in a second mode, wherein said sensing circuit is operable in both said first and second modes.
Claim 6
Dependent Claim
122 words
A semiconductor memory device comprising: a memory array comprising a plurality of electrically erasable nonvolatile memory elements arranged in a matrix and a plurality of word lines, each memory element being selected by one of said word lines and a single data line, gate of said memory element is connected to said word line and drain of said memory element is connected to said data line, sensing circuit reading out information stored in said memory element; and an address decoder specifying one word line in response to an address signal in a first mode, and for grounding all word lines regardless of said address signal in a second mode, wherein said sensing circuit is operable in both said first and second modes.
Claim 7
Dependent Claim
49 words
A semiconductor memory device according to claim 4, wherein in said first mode the memory device is in one of either a write mode or a read mode, and in said second mode the memory device is in one of either an erase mode or a depletion test mode.
Claim 8
Dependent Claim
66 words
A semiconductor memory device comprising: a memory array comprising a plurality of electrically erasable nonvolatile memory elements arranged in a matrix, each memory element having a gate and being selected by a single word line and a single data line; and means for reading out the information stored in said memory element while keeping gates of all of said memory elements at a same predetermined voltage.
Claim 9
Dependent Claim
66 words
A semiconductor memory device comprising: a memory array comprising a plurality of electrically erasable nonvolatile memory elements arranged in a matrix, each memory element having a gate and being selected by a single word line and a single data line; and means for reading out the information stored in said memory element while keeping gates of all of said memory elements at a same predetermined voltage.
Claim 10
Dependent Claim
23 words
A semiconductor memory device according to claim 6, wherein said predetermined voltage is a voltage placing said memory elements in a non-selected state.
Claim 11
Dependent Claim
15 words
A semiconductor memory device according to claim 6, wherein said predetermined voltage is 0 V.
Claim 12
Dependent Claim
94 words
A microcomputer comprising: a CPU having a predetermined information processing function; a nonvolatile memory device; and a system bus for connecting said nonvolatile memory device to said CPU; said nonvolatile memory device comprising: a memory array comprising a plurality of electrically erasable nonvolatile memory elements arranged in a matrix, each memory element having a gate and being selected by a single word line and a single data line; and means for reading out the information stored in said memory element while keeping gates of all of said memory elements on the same predetermined voltage.
Claim 13
Dependent Claim
94 words
A microcomputer comprising: a CPU having a predetermined information processing function; a nonvolatile memory device; and a system bus for connecting said nonvolatile memory device to said CPU; said nonvolatile memory device comprising: a memory array comprising a plurality of electrically erasable nonvolatile memory elements arranged in a matrix, each memory element having a gate and being selected by a single word line and a single data line; and means for reading out the information stored in said memory element while keeping gates of all of said memory elements on the same predetermined voltage.
Claim 14
Dependent Claim
21 words
A microcomputer according to claim 9, wherein said predetermined voltage is a voltage placing said memory elements in a non-selected state.
Claim 15
Dependent Claim
13 words
A microcomputer according to claim 9, wherein said predetermined voltage is 0 V.
References Cited (Backward Citations)
No citation records indexed.
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