Method of manufacturing nonvolatile semiconductor memories

Claim 1

A semiconductor device manufacturing method, in which an interlaid insulating film is formed over a plurality of memory cell transistors, and a wiring formed over the interlaid insulating film is connected with active regions of the memory cell transistors through contact holes, each hole formed in the interlaid film and located between any two adjacent memory cell transistors, characterized by comprising: a step of forming strip shaped first insulating films (2) separately extending in parallel with one another over a surface of a semiconductor substrate (1) of a first conductivity type; a step of forming over the semiconductor substrate (1) and the strip shaped first insulating films (2) a plurality of stacked gate structures extending in parallel with one another and in perpendicular to the strip shaped first insulating films, each stacked gate structure including a second insulating film (3), a floating gate electrode (4), a third insulating film (5), a control gate electrode (6), a fourth electrode (7), and an etching stop film (8) having a slower etching speed than the fourth insulating film (7); a step of self-align removing those portions of each of the first insulating films (2) that are located between any two of the adjacent stacked gate structures extending in parallel with one another and are located above source forming regions with using one end side of each of the stacked gate structures as a part of a mask, so as to expose those portions of the semiconductor substrate (1) that are located at the source forming regions; a step of self-align introducing impurities of a second conductivity type into each of the source forming regions using the one end side of each of the stacked gate structures as a mask; a step of forming fifth insulating films (11) on the side wall portions of each of the stacked gate structures; a step of self-align introducing impurities of the second conductivity type into each of drain forming regions using the other end side of each of the stacked gate structures; a step of self-align exposing those portions of the semiconductor substrate (1) that are located at the drain forming regions with using as parts of a mask the fifth insulating films (11) each formed on the other end side of each of the stacked gate structures; a step of forming conductive layers (19) which contact with surfaces of the exposed drain regions and cover at least those parts of the fifth insulating films (11) that are laid on the walls located at the drain regions of any two adjacent stacked gate structures with corresponding one of the exposed drain regions being interposed between them; a step of forming sixth insulating film (21) on the resultant structure; a step of making contact holes by selectively removing the sixth insulating film (21) with using the conductive layers (19) as stoppers; and a step of forming wiring patterns (24) on those portions of the sixth insulating films that include the contact holes.