Patent EP0412267A2 successfully refreshed from Google Patents.
EP0412267A2
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Asynchronous high-speed data interface
Assignee: International Business Machines Corp
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Filing: 1990-06-23
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Granted: —
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Expires: 2010-06-23
Abstract
Abstract An asynchronous high-speed data interface for coupling a serial channel to a parallel control unit. A first state machine, running synchronously with the channel transmitter clock, controls the filling of a pair of dual-port input buffers (32) in alternating fashion with data bytes from incoming serial frames that have been deserialized and decoded. A second state machine, running synchronously with a second clock that is asynchronous with the channel transmitter clock, controls the transfer of the data bytes from the selected input buffer (32) to one of a pair of output buffers (44) en route to the control unit. Upon detecting the receipt of the third incoming data byte, the first state machine sets a start latch (74), causing the second state machine to begin transferring data from the selected input buffer to the selected output buffer while the input buffer is still being filled. Means are provided for disregarding the data bytes that have been transferred to the selected output buffer if the frame is ultimately aborted.
Inventors
- 👤 Vahe Arpak Minassian
- 👤 Gerald Holt Miracle
- 👤 Richard Andrew Neuner
- 👤 Peter Lloyd Potvin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 13:50
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/16
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
86 words
An asynchronous interface for processing serial frames of data transmitted in synchronism with a first clock, said interface comprising means (28) for deserializing said data synchronously with said first clock, a buffer (32), first means (30) for filling said buffer with said deserialized data synchronously with said first clock, and second means (34) for processing said data from said buffer synchronously with a second clock asynchronous with said first clock, said second means beginning said processing operation before said first means has completed said filling operation.
Claim 2
Dependent Claim
86 words
An asynchronous interface for processing serial frames of data transmitted in synchronism with a first clock, said interface comprising means (28) for deserializing said data synchronously with said first clock, a buffer (32), first means (30) for filling said buffer with said deserialized data synchronously with said first clock, and second means (34) for processing said data from said buffer synchronously with a second clock asynchronous with said first clock, said second means beginning said processing operation before said first means has completed said filling operation.
Claim 3
Dependent Claim
41 words
An interface as in claim 1 in which said buffer comprises a first buffer (32a), said interface further comprising a second buffer (32b), said first means alternatingly filling said first buffer (32a) and then said second buffer (326) with said frames.
Claim 4
Dependent Claim
32 words
An interface as in claim 1 in which said frames contain data bytes and frame delimiter bytes, said first means (30) beginning said filling operation upon the receipt of a data byte.
Claim 5
Dependent Claim
30 words
An interface as in claim 1 in which said second means (34) begins processing data from said buffer (32) upon the filling thereof with a predetermined portion of a frame.
Claim 6
Dependent Claim
41 words
An interface as in any of the above claims in which said buffer (32) is a dual-port buffer, said first means filling said buffer through one port and said second means processing said data from said buffer (32) through another port.
Claim 7
Dependent Claim
46 words
An interface as in further comprising a latch (74), said first means (32) setting said latch (74) upon the receipt of a predetermined number of data bytes from a frame, said second means (34) beginning said processing operation in response to the setting of said latch.
Claim 8
Dependent Claim
46 words
An interface as in further comprising a latch (74), said first means (32) setting said latch (74) upon the receipt of a predetermined number of data bytes from a frame, said second means (34) beginning said processing operation in response to the setting of said latch.
Claim 9
Dependent Claim
30 words
An interface as in claim 1 further comprising storage means (44), said second means (34) transferring successive bytes of said data from said buffer (32) to said storage means (44).
Claim 10
Dependent Claim
77 words
An interface as in claim 7 further comprising a first counter (148) and a second counter (150), said second means (34) incrementing said first counter (148) upon the transfer of each byte of data from said buffer (32) to said storage means (44), said second means (34) transferring the contents of said first counter (148) to said second counter (150) only upon the transfer of a valid frame from said buffer (32) to said storage means (44).
Claim 11
Dependent Claim
121 words
An interface as in claim 7 further comprising a first register (144) and a second register (146), said second means (34) transferring the contents of said first register (144) to said second register (146) before initiating the transfer of said data from said buffer (32) to said storage means (44), said second means (34) incrementing said first register (144) upon the transfer of each byte of data from said buffer (32) to said storage means (44), said first means (30) generating an abort signal upon the detection of an invalid frame, said second means (34) transferring the contents of said second register (146) back to said first register (144) upon the detection of said abort signal from said first means (30).
Claim 12
Dependent Claim
22 words
An interface as in claim 9 in which said storage means (44) has an address input coupled to said first register (144).
Claim 13
Independent Claim
70 words
A method of processing serial frames of data transmitted in synchronism with a first clock, including the steps of deserializing (28) said data synchronously with said first clock, filling a buffer (32) with said deserialized data synchronously with said first clock, and processing said data from said buffer (32) synchronously with a second clock asynchronous with said first clock, said processing step being begun before said filling step is completed.
Claim 14
Independent Claim
70 words
A method of processing serial frames of data transmitted in synchronism with a first clock, including the steps of deserializing (28) said data synchronously with said first clock, filling a buffer (32) with said deserialized data synchronously with said first clock, and processing said data from said buffer (32) synchronously with a second clock asynchronous with said first clock, said processing step being begun before said filling step is completed.
Claim 15
Dependent Claim
23 words
A method as in claim 11 in which a second buffer (32b) is filled with said frames alternatingly with a first buffer (32a).
Claim 16
Dependent Claim
29 words
A method as in claim 11 in which said frames contain data bytes and frame delimiter bytes, said filling step being begun upon the receipt of a data byte.
Claim 17
Dependent Claim
27 words
A method as in claim 11 in which said processing step is begun upon the filling of said buffer (32) with a predetermined portion of a frame.
Claim 18
Dependent Claim
52 words
A method as in claim 11 including the steps of incrementing a first count as successive bytes are written into said buffer, incrementing a second count as successive bytes are processed from said buffer, and halting the further processing of data from said buffer when said second count equals said first count.
Claim 19
Dependent Claim
38 words
A method as in claim 11 in which each of said frames contains n CRC bytes followed by an end-of-frame delimiter, the incrementing of said first count being inhibited for the first n bytes written into said buffer.
Claim 20
Dependent Claim
27 words
A method as in claim 11 in which each of said frames contains an end-of-frame delimiter, said processing step being interrupted upon the receipt of said delimiter.
Claim 21
Dependent Claim
22 words
A method as in claim 17 including the step of checking the validity of said frame following the receipt of said delimiter.
Claim 22
Dependent Claim
21 words
A method as in claim 18 including the step of continuing said processing step upon the detection of a valid frame.
Claim 23
Dependent Claim
21 words
A method as in claim 18 including the step of terminating said processing step upon the detection of an invalid frame.
Claim 24
Dependent Claim
29 words
A method as in claim 11 in which said processing step includes the step of transferring successive bytes of said data from said buffer (32) to storage means (34).
Claim 25
Dependent Claim
30 words
A method as in claim 21 in which said transfer of data from said buffer (32) to said storage means (44) is cancelled upon the detection of an invalid frame.
Claim 26
Dependent Claim
63 words
A method as in claim 21 including the steps of incrementing a first counter (148) upon the transfer of each byte of data from said buffer (32) to said storage means (44) and transferring the contents of said first counter (148) to a second counter (150) only upon the transfer of a valid frame from said buffer (32) to said storage means (44).
Claim 27
Dependent Claim
82 words
A method as in claim 21 including the steps of transferring the contents of a first register (144) to a second register (146) before initiating the transfer of data from said buffer (32) to said storage means (44), incrementing said first register (144) upon the transfer of each byte of data from said buffer (32) to said storage means (44), and transferring the contents of said second register (146) back to said first register (144) upon the detection of an invalid frame.
Claim 28
Dependent Claim
28 words
A method as in claim 24 in which said first register (144) is used to address said storage means (44) for the transfer of data from said buffer.
References Cited (Backward Citations)
No citation records indexed.
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