Patent EP0411747A2 successfully refreshed from Google Patents.
EP0411747A2
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EP
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Multiple instruction decoder
Assignee: Advanced Micro Devices Inc
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Filing: 1990-05-25
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Granted: —
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Expires: 2010-05-25
Abstract
Abstract A multiple instruction decoder is disclosed that employs arbitration to reduce port contentions for M available read ports by N register-operands where M is less than N. In particular, the disclosed multiple instruction decoder includes an input latch for receiving a plurality of logic instructions, wherein the plurality of logic instructions include N register-operand identifiers; arbitration logic coupled to the input latch for arbitrating read port contentions by the N register-operand identifiers for M available read ports (where M is less than N) based on arbitration data corresponding to each of the logic instructions, and for generating control signals indicative thereof; and a multiplexing unit for selectively supplying the N register-operand identifiers to the M available read ports in response to the control signals generated by the arbitration logic.
Inventors
- 👤 William Michael Johnson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 06:07
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/382; G06F9/30098; G06F9/30141; G06F9/3822; G06F9/3824; G06F9/3836; G06F9/3854; G06F9/3856
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
81 words
An apparatus comprising: a. input means for receiving a plurality of logic instructions, wherein said plurality of logic instructions include N register-operand identifiers; b. arbitration means coupled to said input means for arbitrating read port contentions by said N register-operand identifiers for M available read ports where M is less than N, and generating control signals indicative thereof; c. multiplexing means for selectively supplying said N register-operand identifiers to said M available read ports means in response to said control signals.
Claim 2
Independent Claim
81 words
An apparatus comprising: a. input means for receiving a plurality of logic instructions, wherein said plurality of logic instructions include N register-operand identifiers; b. arbitration means coupled to said input means for arbitrating read port contentions by said N register-operand identifiers for M available read ports where M is less than N, and generating control signals indicative thereof; c. multiplexing means for selectively supplying said N register-operand identifiers to said M available read ports means in response to said control signals.
Claim 3
Independent Claim
138 words
An apparatus comprising: a. storage means for storing a plurality of instruction blocks, each instruction block including a plurality of logic instructions; b. predecoding means for retrieving and predecoding said instruction blocks from said storage means, wherein said predecoding means generates arbitration data corresponding to each of said instruction block; c. cache storage means for receiving and storing said instruction blocks and their corresponding arbitration data; d. register means for storing data variables; e. execution means coupled to said register means for executing said logic instructions contained within said instruction blocks; and f. instruction decoding means for receiving said instruction blocks and their corresponding arbitration data from said cache storage means, for decoding the instructions contained within said instruction blocks, and for arbitrating access to said register means based on said arbitration data corresponding to said instruction blocks.
Claim 4
Independent Claim
138 words
An apparatus comprising: a. storage means for storing a plurality of instruction blocks, each instruction block including a plurality of logic instructions; b. predecoding means for retrieving and predecoding said instruction blocks from said storage means, wherein said predecoding means generates arbitration data corresponding to each of said instruction block; c. cache storage means for receiving and storing said instruction blocks and their corresponding arbitration data; d. register means for storing data variables; e. execution means coupled to said register means for executing said logic instructions contained within said instruction blocks; and f. instruction decoding means for receiving said instruction blocks and their corresponding arbitration data from said cache storage means, for decoding the instructions contained within said instruction blocks, and for arbitrating access to said register means based on said arbitration data corresponding to said instruction blocks.
Claim 5
Independent Claim
103 words
An apparatus comprising: a. storage means for storing a plurality of instruction blocks, wherein said instruction blocks inlcude a N register-operands and arbitration data; b. arbitration means coupled to said storage means, for receiving said plurality of instruction blocks from said storage means and arbitrating read part contentions by said N register-operands for M available read buses, which are coupled to M read parts of a storage device, based on said arbitration data; c. multiplexing means coupled to said arbitration means for selectively supplying said N register operands to said M read buses in response to control signals generated by said arbitration means.
Claim 6
Independent Claim
103 words
An apparatus comprising: a. storage means for storing a plurality of instruction blocks, wherein said instruction blocks inlcude a N register-operands and arbitration data; b. arbitration means coupled to said storage means, for receiving said plurality of instruction blocks from said storage means and arbitrating read part contentions by said N register-operands for M available read buses, which are coupled to M read parts of a storage device, based on said arbitration data; c. multiplexing means coupled to said arbitration means for selectively supplying said N register operands to said M read buses in response to control signals generated by said arbitration means.
References Cited (Backward Citations)
No citation records indexed.
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