Patent EP0410413A2 successfully refreshed from Google Patents.
EP0410413A2
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EP
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Semiconductor memory apparatus with a spare memory cell array
Assignee: NEC Corp
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Filing: 1990-07-25
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Granted: —
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Expires: 2010-07-25
Abstract
Abstract In a test of a fabricated semiconductor memory chip, a test control signal is supplied to a test control circuit, so that a spare memory cell array is tested whether spare memory cells are functionable for writing and reading of data. The test control signal is applied to terminals which are used for the supplying of an address signal, etc. For this purpose, the test control signal has a level different from that of the address signal. Therefore, the spare memory cell array can be tested simultaneously with a test of normal memory cell array.
Inventors
- 👤 Mitsuhiro Hamada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 13:50
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/24
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
150 words
A semiconductor memory apparatus with a spare memory cell array, comprising; a normal memory cell array including normal memory cells arranged in a predetermined pattern, data being written into said normal memory cells and read therefrom; a spare memory cell array including spare memory cells arranged in a predetermined pattern, data being written into at least one of said spare memory cells and read therefrom, when at least one of said normal memory cells is faulty; and terminals for supplying control signals including an address signal to a decoder for said normal memory cell array; and a test control circuit for selecting said spare memory cells to be enabled for writing and reading of data, and inhibiting said normal memory cells to be enabled by receiving a test control signal supplied from said terminals, said test control signal being of a logic level different from that of said control signal.
Claim 2
Dependent Claim
150 words
A semiconductor memory apparatus with a spare memory cell array, comprising; a normal memory cell array including normal memory cells arranged in a predetermined pattern, data being written into said normal memory cells and read therefrom; a spare memory cell array including spare memory cells arranged in a predetermined pattern, data being written into at least one of said spare memory cells and read therefrom, when at least one of said normal memory cells is faulty; and terminals for supplying control signals including an address signal to a decoder for said normal memory cell array; and a test control circuit for selecting said spare memory cells to be enabled for writing and reading of data, and inhibiting said normal memory cells to be enabled by receiving a test control signal supplied from said terminals, said test control signal being of a logic level different from that of said control signal.
Claim 3
Dependent Claim
36 words
A semiconductor memory apparatus with a spare memory cell array, according to claim 1, wherein: said control signal is of an ECL level, and said test control signals are of a level outside said ECL level.
Claim 4
Dependent Claim
206 words
A semiconductor memory apparatus with a spare memory cell array, comprising: a normal memory cell array including normal memory cells arranged in a predetermined pattern, data being written into said normal memory cells and read therefrom; a spare memory cell array including spare memory cells arranged in a predetermined pattern, data being written into at least one of said spare memory cells and read therefrom, when at least one of said normal memory cells is faulty; and terminals for supplying a control signal including an address signal to a decoder for said normal memory cell array; an address buffer for holding said address signal to be supplied to said decoder; a faulty address detecting circuit for generating a selecting signal to select said at least one of said spare memory cells, when said address signal held by said address buffer is coincided with an address of a faulty normal memory cell; and a test control circuit for selecting said spare memory cells to be enabled for writing and reading of data, and inhibiting said normal memory cells to be enabled by receiving a test control signal supplied form said terminals, said test control signal being of a logic level different from that of said control signal.
Claim 5
Dependent Claim
206 words
A semiconductor memory apparatus with a spare memory cell array, comprising: a normal memory cell array including normal memory cells arranged in a predetermined pattern, data being written into said normal memory cells and read therefrom; a spare memory cell array including spare memory cells arranged in a predetermined pattern, data being written into at least one of said spare memory cells and read therefrom, when at least one of said normal memory cells is faulty; and terminals for supplying a control signal including an address signal to a decoder for said normal memory cell array; an address buffer for holding said address signal to be supplied to said decoder; a faulty address detecting circuit for generating a selecting signal to select said at least one of said spare memory cells, when said address signal held by said address buffer is coincided with an address of a faulty normal memory cell; and a test control circuit for selecting said spare memory cells to be enabled for writing and reading of data, and inhibiting said normal memory cells to be enabled by receiving a test control signal supplied form said terminals, said test control signal being of a logic level different from that of said control signal.
Claim 6
Dependent Claim
43 words
A semiconductor memory apparatus with a spare memory cell array, according to claim 3, wherein: said address buffer is of an ECL circuit; said address signal is of an ECL level; said test control signal is of a level outside said ECL level.
Claim 7
Dependent Claim
82 words
A semiconductor memory apparatus with a spare memory cell array, according to claim 3, wherein: said faulty address delecting circuit, comprises: means for storing an address of a faulty memory cell in said normal memory cell array; means for comparing said address signal held by said address buffer with said address of said faulty memory cell; and means for generating said selecting signal, when said address signal held by said address buffer is coincided with said address of said faulty memory cell.
References Cited (Backward Citations)
No citation records indexed.
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