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EP0410382A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Data transfer controller using direct memory access method

Assignee: NEC Corp
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Filing: 1990-07-24
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Granted: —
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Expires: 2010-07-24
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Abstract

Abstract A data transfer controller comprises a first register for temporarily storing address information relative to a predetermined address of a memory area used for a DMA data transfer, a second register for storing a number of data to be transferred, means for performing a DMA data transfer between said memory area and a peripheral unit by use of said first and second registers, a third register for storing data used for accessing said memory area, means for updating the data of said third register each time an access to said memory area using said third register and being different from an access for said DMA data transfer is performed, storage means for storing data representative of a number of data stored in said memory area, and means for changing the data of said storage means in one direction each time said DMA data transfer is performed and for changing the data of said storage means in an opposite direction each time said access to said memory area using said third register is performed.

Inventors

  • 👤 Tsuyoshi C/O Nec Corporation Katayose
  • 👤 Yukio C/O Nec Corporation Maehashi

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 19:40
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28

Claims Analysis

Total Claims: 1
Claim 1
Independent Claim 173 words
A data transfer controller comprising a first register for temporarily storing address information relative to a predetermined address of a memory area used for a DMA data transfer, a second register for storing a number of data to be transferred, means for performing a DMA data transfer between said memory area and a peripheral unit by use of said first and second registers, a third register for storing data used for accessing said memory area, means for updating the data of said third register each time an access to said memory area using said third register and being different from an access for said DMA data transfer is performed, storage means for storing data representative of a number of data stored in said memory area, and means for changing the data of said storage means in one direction each time said DMA data transfer is performed and for changing the data of said storage means in an opposite direction each time said access to said memory area using said third register is performed.

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