Patent EP0409556A2 successfully refreshed from Google Patents.
EP0409556A2
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EP
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Data processing device for preventing inconsistency of data stored in main memory and cache memory
Assignee: Fujitsu Ltd
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Filing: 1990-07-17
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Granted: —
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Expires: 2010-07-17
Abstract
Abstract A comparing unit (2) compares an address of data written into a main memory (M) by an external device (MPU2, DMAC) with an address of data stored in a cache memory, and a masking unit (3) masks specific bits obtained by a result in said address comparing unit (3). An invalidating unit (1) invalidates data stored in the cache memory corresponding to the specific bits masked by the masking unit (3). Therefore, inconsistency between the main memory and the cashe memory can be prevented, even when the data are transferred by using a block transfer process.
Inventors
- 👤 Atsushi Fujihira
- 👤 Takeshi Kitahara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:55
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0835; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
131 words
An address monitoring device for monitoring a process of writing to a main memory (M) by an external device (MPU2, DMAC), and when an address corresponding to data stored in a cache memory is detected in said write process, for invalidating stored address data in said cache memory corresponding to said detected write address, wherein said address monitoring device comprises masking means (3) for specifying one or more specific bits within the address of data stored in the cache memory which are to be compared with the address of data written into the main memory (M); comparing means (2) for comparing the specified bits of each address; and invalidating means (1) for invalidating data stored in the cache memory, when the comparing means (2) finds that the compared bits are concidental.
Claim 2
Dependent Claim
131 words
An address monitoring device for monitoring a process of writing to a main memory (M) by an external device (MPU2, DMAC), and when an address corresponding to data stored in a cache memory is detected in said write process, for invalidating stored address data in said cache memory corresponding to said detected write address, wherein said address monitoring device comprises masking means (3) for specifying one or more specific bits within the address of data stored in the cache memory which are to be compared with the address of data written into the main memory (M); comparing means (2) for comparing the specified bits of each address; and invalidating means (1) for invalidating data stored in the cache memory, when the comparing means (2) finds that the compared bits are concidental.
Claim 3
Dependent Claim
33 words
An address monitoring device as claimed in claim 1, wherein said address monitoring device further comprises a mask bit determining means (4) for determining a bit number for masking in said specific bits.
Claim 4
Dependent Claim
47 words
An address monitoring device as claimed in claim 2, wherein said mask bit determining means (4) comprises a plurality of logic gate circuits, and the bit number for masking in said specific bits is determined by masking control signals (BS0, BS1) supplied to said logic gate circuits.
Claim 5
Dependent Claim
45 words
An address monitoring device as claimed in claim 2, wherein said mask bit determining means (4) comprises a masking address control register (6), and the bit number for masking in said specific bits is determined by data stored in said masking address control register (6).
Claim 6
Dependent Claim
41 words
An address monitoring device as claimed in claim 2, wherein said mask bit determining means (4) determines the bit number for masking in said specific bits in accordance with a data length of said data written into said main memory (M).
Claim 7
Dependent Claim
26 words
An address monitoring device as claimed in any preceding claim, wherein said data are written into said main memory (M) by using a block transfer process.
Claim 8
Dependent Claim
27 words
An address monitoring device as claimed in any preceding claim, wherein said comparing means (2) and said masking means (3) comprise a plurality of logic gate circuits.
Claim 9
Dependent Claim
26 words
An address monitoring device as claimed in any preceding claim, wherein said invalidating means (1) comprises a tag memory (1) including a valid bit portion (V).
Claim 10
Dependent Claim
68 words
A data processing device comprising a bus control unit (81) for transferring data among a main memory (M) and external devices (MPU2, DMAC) through buses; a memory control unit (82) include a cache memory (821); an instruction control unit (83) for controlling fetching and decoding of instructions; an instruction execution unit (84) for executing said instructions; and an address monitoring device according to any of the preceding claims.
Claim 11
Dependent Claim
55 words
A data processing device (MPU1) as claimed in claim 9, wherein said external device (MPU2, DMAC) writing data into said main memory (M) is another data processing device (MPU2) or a direct memory access controller (DMAC), and is connected to said data processing device (MPU1) and said main memory (M) through a system bus (SB).
Claim 12
Dependent Claim
47 words
A data processing system having a data processing device (MPU1) according to claim 9 or claim 10, external devices (MPU2, DMAC), a main memory (M), and a system bus (SB) for connecting said data processing device (MPU1), said external devices (MPU2, DMAC), and said main memory (M).
Claim 13
Dependent Claim
58 words
A monolithic microprocessor formed in a single semiconductor body, wherein said monolithic microprocessor comprises a built-in cache memory (821); an instruction execution means (84), for executing an instruction and outputting a write address for accessing the built-in cache memory (821) or a main memory (M); and an address monitoring device according to any of claims 1 to 8.
Claim 14
Dependent Claim
53 words
A monolithic microprocessor (MPU1) as claimed in claim 12, wherein the external device (MPU2, DMAC) writing data into the main memory (M) is another monolithic microprocessor (MPU2) or a direct memory access controller (DMAC), and is connected to the data processing device (MPU1) and the main memory (M) through a system bus (SB).
References Cited (Backward Citations)
No citation records indexed.
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