Bit field logic operation unit and monolithic microprocessor comprising said unit

Claim 2

A bit field logic operation unit comprising: a logic operation means (38) for performing a specified logic operation on source data (A) and destination data (B) to output a logic operation result (E); a mask pattern generation means (40) for simultaneously generating a bit mask pattern (MPG) from mask information (D, M) in parallel with the operation of the logic operation means (38); and a bit map operation means (42) for selecting either the logic operation result (E) or the destination data (B) in each bit position according to the bit mask pattern (MPG) to output a masked logic operation result (S).

Claim 3

A bit field logic operation unit as claimed in claim 1, wherein the logic operation means (38) and the mask pattern generation means (40) are constituted by dynamic circuit constructions wherein the processes are performed in a preset period to preset potentials of circuit nodes and an active period to output processed data according to input signals.

Claim 4

A bit field logic operation unit as claimed in claim 2, wherein the preset period of the logic operation means and the preset period of the mask pattern generation means are carried out simultaneously.

Claim 5

A bit field logic operation unit as claimed in claim 3, wherein the bit map operation means is also constituted in the dynamic circuit construction.

Claim 6

A bit field logic operation unit as claimed in claim 4, wherein the active period of the logic operation means (38) and the mask pattern generation means (40) and the preset period of the bit map operation means (42) are carried out simultaneously.

Claim 7

A bit field logic operation unit as claimed in claim 5, wherein signals (U, L, N) for specifying a masking mode are input to the bit map operation means (42′) and an operation mode of the bit map operation means (42′) is altered according to the signals.

Claim 8

A monolithic microprocessor comprising: an instruction receiving means (10, 16) for receiving an instruction; a control means (18) for generating control signals according to the instruction transferred from the instruction receiving means (10, 16); an arithmetic logic unit (26) for performing an arithmetic logic operation in response to the control signals; and a bit field logic operation unit (28) connected to the control means (18) and for performing a logic operation on bit fields of parts of a source data (A) and a destination data (B) both of which comprise a plurality of bits, in response to a bit manipulation instruction, wherein the bit field logic operation unit (28) comprises: a logic operation means (38) for performing a specified logic operation on source data (A) and destination data (B) to output a logic operation result (E); a mask pattern generation means (40) or simultaneously generating a bit mask pattern (MPG) from mask information (D, M) in parallel with the operation of the logic operation means (38); and a bit map operation means (42) for selecting either the logic operation result (E) or the destination data (B) in each bit position according to the bit mask pattern (MPG) to output a masked logic operation result (S).

Claim 9

A monolithic microprocessor comprising: an instruction receiving means (10, 16) for receiving an instruction; a control means (18) for generating control signals according to the instruction transferred from the instruction receiving means (10, 16); an arithmetic logic unit (26) for performing an arithmetic logic operation in response to the control signals; and a bit field logic operation unit (28) connected to the control means (18) and for performing a logic operation on bit fields of parts of a source data (A) and a destination data (B) both of which comprise a plurality of bits, in response to a bit manipulation instruction, wherein the bit field logic operation unit (28) comprises: a logic operation means (38) for performing a specified logic operation on source data (A) and destination data (B) to output a logic operation result (E); a mask pattern generation means (40) or simultaneously generating a bit mask pattern (MPG) from mask information (D, M) in parallel with the operation of the logic operation means (38); and a bit map operation means (42) for selecting either the logic operation result (E) or the destination data (B) in each bit position according to the bit mask pattern (MPG) to output a masked logic operation result (S).

Claim 10

A monolithic microprocessor as claimed in claim 7, wherein the logic operation means (38), the mask pattern generation means (40), and the bit map operation means (42) are constituted by dynamic circuit constructions wherein the processes are performed in a preset period to preset a potential of circuit nodes and an active period to output processed data according to input signals, the preset period and the active period of the logic operation means (38) overlap the present period and the active period of the mask pattern generation means (40), respectively, and the active periods of the logic operation means (38) and the mask pattern generation means (40) overlap the preset period of the bit map operation means (42).

Claim 11

A monolithic microprocessor as claimed in claim 7, wherein the mask pattern generation means (40) receives a mask data (D) and a size data (M) and generates the bit mask pattern (MPG) for a variable length bit field specified by the bit manipulation instructions.

Claim 12

A monolithic microprocessor as claimed in claim 7, wherein the arithmetic logic unit (26) performs operations except for the bit manipulation instruction.

Claim 13

A monolithic microprocessor as claimed in claim 7, further comprising a bus means (32, 34, 36) connected to the bit field logic operation unit (28) and the arithmetic logic unit (26), wherein the source data (A), the destination data (B), and the masked logic operation result (S) are transferred through the bus means (32, 34, 36).