Patent US6316980B1 successfully refreshed from Google Patents.
Patent EP0407173A2 successfully refreshed from Google Patents.
EP0407173A2
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1990-07-04
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Granted: —
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Expires: 2010-07-04
Abstract
Abstract A semiconductor memory device having a test mode function and a plurality of memory blocks (1-1 to 1-8) each having memory cells arranged in an array (1) and a method for testing the device. The device includes a write/read control circuit (3) for writing identical data in each memory cell of the plurality of memory blocks, and in a test mode simultaneously reading data of one bit from each of the plurality of memory blocks. A test circuit (6,8,9) detects coincidence or non-coincidence of the read bits and outputs a result of the detection. A gate circuit (7) sequentially outputs the read bits one by one when the result is the non-coincidence. As a result, an address of a "failing" bit can be detected to facilitate a failure analysis.
Inventors
- 👤 Toru Kono
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 07:28
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/44; G11C29/18; G11C29/26; G11C29/30; G11C29/34
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
203 words
A semiconductor memory device having normal and test modes, comprising: a memory cell array (1) divided into a plurality of memory blocks (1-1 to 1-8) each having memory cells arranged in rows and columns; a write/read control circuit (3) operatively connected to said memory cell array and responsive to external address signals (ADD) and control signals (CS), for writing identical data in each of said memory cells of said memory cell array and, in said test mode, simultaneously reading data of one bit from each of said plurality of memory blocks; and a test circuit (6, 8, 9) operatively connected to said memory cell array for detecting coincidence or non-coincidence of a plurality of said simultaneously read bits and outputting a result of the detection; characterised by a gate circuit (7) operatively connected to said memory cell array, for passing, under given conditions, data of a plurality of bits read from said plurality of memory blocks in the said test mode and in that the test circuit (6, 8, 9) is connected to the write/read control circuit and gate circuit and is arranged when the result is non-coincidence, to control said gate circuit sequentially to output said plurality of bits bit by bit.
Claim 2
Dependent Claim
203 words
A semiconductor memory device having normal and test modes, comprising: a memory cell array (1) divided into a plurality of memory blocks (1-1 to 1-8) each having memory cells arranged in rows and columns; a write/read control circuit (3) operatively connected to said memory cell array and responsive to external address signals (ADD) and control signals (CS), for writing identical data in each of said memory cells of said memory cell array and, in said test mode, simultaneously reading data of one bit from each of said plurality of memory blocks; and a test circuit (6, 8, 9) operatively connected to said memory cell array for detecting coincidence or non-coincidence of a plurality of said simultaneously read bits and outputting a result of the detection; characterised by a gate circuit (7) operatively connected to said memory cell array, for passing, under given conditions, data of a plurality of bits read from said plurality of memory blocks in the said test mode and in that the test circuit (6, 8, 9) is connected to the write/read control circuit and gate circuit and is arranged when the result is non-coincidence, to control said gate circuit sequentially to output said plurality of bits bit by bit.
Claim 3
Dependent Claim
78 words
A device as set forth in claim 1, comprising a plurality of pairs of data buses corresponding to the number of said plurality of memory blocks, wherein said write/read control circuit (3) includes a decoding circuit (52, 54) for selecting one memory cell in each of said plurality of memory blocks according to said address signal, and a plurality of column gates (550 to 557) for transmitting data of said selected memory cells to said data buses correspondingly.
Claim 4
Dependent Claim
68 words
A device as set forth in claim 2, comprising a pair of common data lines (DL, DLX) connected to an external terminal (I/O), wherein said gate circuit (7) has a plurality of pairs of transistors (130, 140; ...; 137, 147) connected between respective pairs of said data buses and said pair of data lines, said pairs of transistors being turned ON under the control of said test circuit.
Claim 5
Dependent Claim
35 words
A device as set forth in claim 3, wherein said test circuit comprises a first signal-generating circuit (G3, 6) for sequentially generating gate signals (d0 to d7) for turning ON said pairs of transistors, respectively.
Claim 6
Dependent Claim
100 words
A device as set forth in claim 4, wherein said test circuit comprises a plurality of logic gates for respectively detecting, in said test mode, whether or not data of two bits output to two pairs of said plurality of pairs of data buses coincide with each other, a plurality of pairs of transistors (170, 171; ... ; 176, 177) for transmitting results of the detection, respectively, to said pair of data lines (DL, DLX), and a second signal-generating circuit (G2, 8) for sequentially generating gate signals (e0 to e3) for turning ON said plurality of pairs of transistors, respectively.
Claim 7
Dependent Claim
85 words
A device as set forth in claim 5, wherein said test circuit comprises a circuit (9) for detecting, in said test mode, whether or not data of a plurality of bits output to said plurality of pairs of data buses coincide with one another, a pair of transistors (23, 33) for transmitting a result of the detection to said pair of data lines (DL, DLX), and a third signal-generating circuit (G1, 8) for generating a gate signal (f0) for turning ON said pair of transistors.
Claim 8
Dependent Claim
57 words
A device as set forth in claim 6, further comprising a control circuit (C, 5) for switching said test mode and normal mode from one to the other according to address signals (ADD0 to ADD10) and control signals (WEX, CASX, RASX), said first, second and third signal-generating circuits being separately activated by outputs of said control circuit.
Claim 9
Dependent Claim
70 words
A device as set forth in claim 7, wherein each of said first and second signal-generating circuits (G3, G2) comprises a decoder (61, 71) for decoding address information (A2, A1) in response to an activating signal from said control circuit, and a circuit (62, 72) for generating said gate signals (d0 to d7, e0 to e3) in response to the decoded information and an external column address strobe signal (CASX).
Claim 10
Dependent Claim
214 words
A semiconductor memory device having normal and test modes, comprising: a memory cell array (1) divided into 2 N memory blocks (1-1 to 1-8) each having memory cells arranged in a matrix; a redundant means (2, 4) for simultaneously replacing data of 2 M bits among 2 N bits in said 2 N memory blocks, where 2 N > 2 M ; a write/read control circuit (3) operatively connected to said memory cell array and responsive to external address signals (ADD) and control signals (CS), for writing identical data in each of said memory cells of said memory cell array and, in the test mode, simultaneously reading data of one bit from each of said 2 N memory blocks; a gate circuit (7) operatively connected to said memory cell array, for passing, under given conditions, data of 2 N bits read from said 2 N memory blocks in said test mode; and a test circuit (6, 8, 9) operatively connected to said memory cell array, write/read control circuit and gate circuit, for detecting coincidence or non-coincidence of the 2 N bits of said read data, outputting a result of the detection and, when the result is the non-coincidence, controlling said ate circuit to sequentially output said data of 2 N bits bit by bit.
Claim 11
Dependent Claim
214 words
A semiconductor memory device having normal and test modes, comprising: a memory cell array (1) divided into 2 N memory blocks (1-1 to 1-8) each having memory cells arranged in a matrix; a redundant means (2, 4) for simultaneously replacing data of 2 M bits among 2 N bits in said 2 N memory blocks, where 2 N > 2 M ; a write/read control circuit (3) operatively connected to said memory cell array and responsive to external address signals (ADD) and control signals (CS), for writing identical data in each of said memory cells of said memory cell array and, in the test mode, simultaneously reading data of one bit from each of said 2 N memory blocks; a gate circuit (7) operatively connected to said memory cell array, for passing, under given conditions, data of 2 N bits read from said 2 N memory blocks in said test mode; and a test circuit (6, 8, 9) operatively connected to said memory cell array, write/read control circuit and gate circuit, for detecting coincidence or non-coincidence of the 2 N bits of said read data, outputting a result of the detection and, when the result is the non-coincidence, controlling said ate circuit to sequentially output said data of 2 N bits bit by bit.
Claim 12
Dependent Claim
58 words
A device as set forth in claim 9, wherein said test circuit comprises a means for compressing said data of 2 M bits to form 2 M -bit-compressed data and successively outputting 2 M -bit-compressed data 2 L times in response to given control signals (e0 to e3), where 2 N = 2 M . 2 L .
Claim 13
Dependent Claim
59 words
A semiconductor memory device according to any one of the preceding claims in which the test circuit (6,8,9) is arranged to output the result of the detection of coincidence or non-coincidence to a single terminal and to control said gate circuit to sequentially output said plurality of bits bit by bit to said single terminal during the test mode.
Claim 14
Independent Claim
106 words
A method for testing a semiconductor memory device including a plurality of memory blocks (1-1 to 1-8) each having memory cells arranged in rows and columns, comprising the steps of: writing identical data in each of said memory cells of said plurality of memory blocks; simultaneously reading data of one bit from each of said plurality of memory blocks; detecting coincidence or non-coincidence of a plurality of said simultaneously read bits and outputting a result of the detection; characterised by sequentially outputting said plurality of bits bit by bit when the result of the detection is the non-coincidence, thereby detecting an address of a failing bit.
Claim 15
Independent Claim
106 words
A method for testing a semiconductor memory device including a plurality of memory blocks (1-1 to 1-8) each having memory cells arranged in rows and columns, comprising the steps of: writing identical data in each of said memory cells of said plurality of memory blocks; simultaneously reading data of one bit from each of said plurality of memory blocks; detecting coincidence or non-coincidence of a plurality of said simultaneously read bits and outputting a result of the detection; characterised by sequentially outputting said plurality of bits bit by bit when the result of the detection is the non-coincidence, thereby detecting an address of a failing bit.
Claim 16
Dependent Claim
33 words
A method as set forth in claim 12, wherein said step of sequentially outputting said plurality of bits bit by bit is carried out by sequentially changing bits of an address information (A2).
Claim 17
Dependent Claim
37 words
A method as set forth in claim 12, wherein said step of sequentially outputting said plurality of bits bit by bit is carried out by sequentially changing a logic level of a column address strobe signal (CASX).
Claim 18
Independent Claim
128 words
A method for testing a semiconductor memory device including a plurality of memory blocks (1-1 to 1-8) each having memory cells arranged in a matrix and a redundant means (2, 4) for simultaneously replacing data in part of said plurality of memory blocks. comprising the steps of: writing identical data in each of said memory cells of said plurality of memory blocks in which the redundant replacement has been carried out; simultaneously reading data of one bit from each of said plurality of memory blocks; detecting coincidence or non-coincidence of said simultaneously read bits and outputting a result of the detection; characterised by sequentially outputting said read bits bit by bit when the resu!t of the detection is the non-coincidence, thereby detecting an address of a failing bit.
Claim 19
Independent Claim
128 words
A method for testing a semiconductor memory device including a plurality of memory blocks (1-1 to 1-8) each having memory cells arranged in a matrix and a redundant means (2, 4) for simultaneously replacing data in part of said plurality of memory blocks. comprising the steps of: writing identical data in each of said memory cells of said plurality of memory blocks in which the redundant replacement has been carried out; simultaneously reading data of one bit from each of said plurality of memory blocks; detecting coincidence or non-coincidence of said simultaneously read bits and outputting a result of the detection; characterised by sequentially outputting said read bits bit by bit when the resu!t of the detection is the non-coincidence, thereby detecting an address of a failing bit.
References Cited (Backward Citations)
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