Patent EP0405850A2 successfully refreshed from Google Patents.
EP0405850A2
Expired / Lapsed
EP
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Dielectric formation process and devices produced thereby
Assignee: AT&T Inc
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Filing: 1990-06-22
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Granted: —
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Expires: 2010-06-22
Abstract
Abstract The occurrence of low-density regions in conformal layers deposited between raised topographic features (for example, metal runners) on an integrated circuit is prevented or reduced by the inventive process. The low-density regions (termed "soft oxides" when the conformal layer is an oxide of silicon), are preferentially attacked by subsequent etching procedures and produce undesired trenches which interfere with subsequent processing. The inventive process forms spacers, or fillets (60), between the raised topographic features (15). Then a conformal layer (79), such as dielectric formed from TEOS, may be deposited without causing the formation of low-density regions.
Inventors
- 👤 Alain Simon Harrus
- 👤 Graham William Hills
- 👤 Morgan Jones Thoma
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 10:00
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; H10W20/071; H10W20/074; H10W20/077; H10W20/098; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/66; H10P14/668; H10P14/6681; H10P14/6684; H10P14/6686; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
76 words
A method of semiconductor integrated circuit fabrication comprising: fortming a plurality of raised topographic features upon a substrate, said topographic features having sidewalls, and with each adjacent pair of features defining a space therebetween; depositing a first layer over said features; AND CHARACTERIZED BY the further steps of etching said first layer to form spacers adjacent to said sidewalls; depositing a second layer having conformal properties, said second layer contacting said spacers and filling said space.
Claim 2
Independent Claim
76 words
A method of semiconductor integrated circuit fabrication comprising: fortming a plurality of raised topographic features upon a substrate, said topographic features having sidewalls, and with each adjacent pair of features defining a space therebetween; depositing a first layer over said features; AND CHARACTERIZED BY the further steps of etching said first layer to form spacers adjacent to said sidewalls; depositing a second layer having conformal properties, said second layer contacting said spacers and filling said space.
Claim 3
Dependent Claim
16 words
The method of claim 1 further including the step of anisotropically etching back said second layer.
Claim 4
Dependent Claim
27 words
The method of claim 1 wherein said second layer is deposited by decomposition of a material chosen from the group consisting of TEOS, TMOS, DADBS, and TMCTS.
Claim 5
Dependent Claim
27 words
The method of claim 1 wherein said first layer is deposited by decomposition of a material chosen from the group consisting of TEOS, TMOS, DADBS, and TMCTS.
Claim 6
Dependent Claim
12 words
The method of claim 1 wherein said raised topographic features are conductors.
Claim 7
Dependent Claim
25 words
The method of claim 5 wherein said conductors are made from materials chosen from the group consisting of aluminum, aluminum-silicon mixtures, tungsten, polysilicon, and silicides.
Claim 8
Dependent Claim
128 words
The method of claim 1 wherein said raised topographic features are runners each of said runners having a sidewall and a top and wherein said first layer is formed by depositing TEOS in a plasma; and wherein said etching step is an anisotropic etching step which forms spacers with curved sides and permits a portion of said first TEOS layer to remain on the said tops of said runners and upon said substrate; and wherein said second layer is formed by depositing TEOS in a plasma over said spacers and over said remaining portion of said first layer of TEOS which is upon said tops of said runners and upon said substrate; and further wherein said second layer is anisotropically etched, the tops of said runners remaining covered.
References Cited (Backward Citations)
No citation records indexed.
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