Patent EP0405833A2 successfully refreshed from Google Patents.
EP0405833A2
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EP
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Programmable logic level input buffer
Assignee: AT&T Inc
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Filing: 1990-06-20
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Granted: —
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Expires: 2010-06-20
Abstract
Abstract An integrated circuit input buffer is adapted to operate at either of two input levels, typically either TTL or CMOS logic levels. This is accomplished by switching an additional transistor (e.g. 15) into a path between the output node (e.g. 12) and a power supply voltage (e.g. V DD ), thereby changing the ratio of the pull-up to pull-down devices (e.g. 14, 13). The desired input level may be selected after the manufacture of the device, as by applying a voltage to a package terminal, or by programming a register during operation of the integrated circuit.
Inventors
- 👤 James V. Morgan, Jr.
- 👤 Glen E. Offord
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 18:49
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018585
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
145 words
An integrated circuit comprising at least one input buffer having an input node (11) and an output node (12), the buffer comprising a first input transistor (141 of a given conductivity type having a gate coupled to the input node, and being adapted to pull the output node toward a first power supply voltage (V DD ), a second transistor (13) adapted to pull the output node toward a second power supply voltage (V SS ), the input switching level of the buffer being influenced by the ratio of the inpedances of the first and second transistors, and CHARACTERIZED BY a third transistor (15) of the given conductivity type, and means (16) for switching the channel of the third transistor into a path between the output node and a power supply voltage (V DD ), whereby the input switching level of the buffer is selected.
Claim 2
Dependent Claim
145 words
An integrated circuit comprising at least one input buffer having an input node (11) and an output node (12), the buffer comprising a first input transistor (141 of a given conductivity type having a gate coupled to the input node, and being adapted to pull the output node toward a first power supply voltage (V DD ), a second transistor (13) adapted to pull the output node toward a second power supply voltage (V SS ), the input switching level of the buffer being influenced by the ratio of the inpedances of the first and second transistors, and CHARACTERIZED BY a third transistor (15) of the given conductivity type, and means (16) for switching the channel of the third transistor into a path between the output node and a power supply voltage (V DD ), whereby the input switching level of the buffer is selected.
Claim 3
Dependent Claim
31 words
An integrated circuit as claimed in claim 1 wherein the second transistor (13) has the opposite conductivity type to the given type, and has its gate coupled to the input node.
Claim 4
Dependent Claim
29 words
An integrated circuit as claimed in claim 1 wherein the second transistor (34) has the given conductivity type, and has its gate coupled to the second power supply voltage.
Claim 5
Dependent Claim
45 words
An integrated circuit as claimed in claim 1 or 2 wherein the means for switching comprises a fourth transistor (16) of the given conductivity type having its source coupled to the first power supply, and its drain coupled to the source of the third transistor.
Claim 6
Dependent Claim
45 words
An integrated circuit as claimed in claim 1 or 3 wherein the means for switching comprises a fourth transistor (30) of the given conductivity type having its source coupled to the drain of the third transistor, and its drain coupled to the common output node.
Claim 7
Dependent Claim
25 words
An integrated circuit as claimed in any preceding claim wherein the means for switching is controllable by a signal generated externally to the integrated circuit.
Claim 8
Dependent Claim
28 words
An integrated circuit as claimed in any one of claims 1 to 5 wherein the means for switching is controllable by a signal generated on the integrated circuit.
Claim 9
Dependent Claim
29 words
An integrated circuit as claimed in claim 7 wherein the means for switching is controllable by a signal that is generated by a comparator located on the integrated circuit.
Claim 10
Dependent Claim
29 words
An integrated circuit as claimed in claim 7 wherein the means for switching is controllable by a signal that is generated by a register located on the integrated circuit.
References Cited (Backward Citations)
No citation records indexed.
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