EP0404444A1 — Apparatus and method for performing spike analysi…

Claim 1

Independent Claim 97 words

A logic circuit simulator arranged for detecting a spike condition at the output of a simulated gate, wherein a spike condition is defined as an output pulse resulting from gate input signals occurring faster than the propagation delay of the gate, comprising a plurality of autonomous devices arranged for parallel operation, with each device being designed to perform part of the overall simulation function, characterized in that one of the devices is responsive to signals representing the times of occurrence of gate input stimuli and to gate propagation delay data primarily for performing the spike analysis function.

Claim 2

Dependent Claim 97 words

A logic circuit simulator arranged for detecting a spike condition at the output of a simulated gate, wherein a spike condition is defined as an output pulse resulting from gate input signals occurring faster than the propagation delay of the gate, comprising a plurality of autonomous devices arranged for parallel operation, with each device being designed to perform part of the overall simulation function, characterized in that one of the devices is responsive to signals representing the times of occurrence of gate input stimuli and to gate propagation delay data primarily for performing the spike analysis function.

Claim 3

Dependent Claim 35 words

The simulator of claim 1 wherein a first said device performs the function of gate output signal scheduling in response to gate input stimuli for transmitting messages containing said signals to the spike analyzing device.

Claim 4

Dependent Claim 30 words

The simulator of claim 2 further characterized in that the first device and the spike analyzing device are programmable processors programmed to perform their specified function of the overall simulation.

Claim 5

Dependent Claim 18 words

The simulator of claim 2 or claim 3 wherein the devices are arranged in a series connected pipeline.

Claim 6

Dependent Claim 36 words

The simulator of claim 4 wherein the spike analyzing device further comprises means responsive to the detection of a spike condition for transmitting into the pipeline signals indicating the scheduling of an unknown gate output event.

Claim 7

Dependent Claim 51 words

The simulator of claim 2 or claim 3 further characterized by separate time wheels in the signal scheduling device and in the spike analyzing device, each time wheel having a plurality of time slots for storing scheduled times of occurrences of gate output events in response to the gate input stimuli.

Claim 8

Dependent Claim 90 words

The simulator of claim 6 wherein the spike analyzing device further comprises first means responsive to the receipt of a scheduled gate output event from the signal scheduling device for scheduling the event in an appropriate time slot of its time wheel, second means for determining if an output event is already scheduled for the gate and third means responsive to the second means for determining if an already scheduled event and the present event results in an output pulse of duration less than the propagation delay of the gate.

Claim 9

Dependent Claim 28 words

The simulator of claim 7 wherein the spike analyzing device further comprising means for storing the propagation delay of a gate as a delay weighted by a variable.

Claim 10

Dependent Claim 56 words

The simulator of claim 8 wherein the means for storing further comprises means for separately storing weighted gate rise time delay and weighted gate fall time delay and means responsive to the direction of transition of a scheduled output pulse for accessing the appropriate one of the rise and fall delays for performing the spike analysis.

Claim 11

Independent Claim 123 words

A method of detecting spike conditions at the outputs of simulated gates in a logic circuit simulator, wherein a spike condition is defined as an output pulse resulting from gate input signals occurring faster than the propagation delay of the gate, in which the simulator comprises a plurality of autonomous devices arranged for parallel operation, with each device being designed to perform part of the overall simulation function, said method including the step of scheduling gate output transitions in a first one of the devices in response to circuit input stimuli and said method being characterized by the step of performing the spike detection function in a second one of the devices in response to signals from the first one of the devices.

Claim 12

Independent Claim 123 words

A method of detecting spike conditions at the outputs of simulated gates in a logic circuit simulator, wherein a spike condition is defined as an output pulse resulting from gate input signals occurring faster than the propagation delay of the gate, in which the simulator comprises a plurality of autonomous devices arranged for parallel operation, with each device being designed to perform part of the overall simulation function, said method including the step of scheduling gate output transitions in a first one of the devices in response to circuit input stimuli and said method being characterized by the step of performing the spike detection function in a second one of the devices in response to signals from the first one of the devices.

Claim 13

Dependent Claim 88 words

The method of claim 10 further comprising the step of determining in the spike detecting device if another output event is already scheduled for the gate in response to signals from the scheduling device specifying an output event, determining if the two events result in gate input transitions that occur in less than the propagation delay of the gate, and, if so, scheduling in the time wheel of the spike detecting device a gate output event of unknown state beginning at the time of the first scheduled event.

Claim 14

Dependent Claim 74 words

The method of claim 11 further characterized by the steps of maintaining separate time wheels in the signal scheduling device and in the spike detecting device, each time wheel having a plurality of time slots, storing scheduled times of occurrences of gate output events in response to the gate input stimuli in the time wheel of the signal scheduling device and storing scheduled spike conditions in the time wheel of the spike detecting device.

Claim 15

Dependent Claim 47 words

The method of claim 12 further comprising the steps of sequentially accessing the time slots of a time wheel in the signal scheduling device and the spike detecting device and transmitting signals, at the appropriate times, to other device gate events scheduled in the respective time wheels.

Claim 16

Dependent Claim 34 words

The method of claim 13 further comprising the step of storing the propagation delay of a gate in the spike detecting device as a delay weighted by a variable for purposes of spike detection.

Claim 17

Dependent Claim 63 words

15 . The simulator of claim 13 wherein the step of storing further comprises separately storing weighted gate rise time delays and weighted gate fall time delays and the spike detecting device further comprises the step of accessing the appropriate one of the rise and fall delays for performing the spike detection responsive to the direction of transition of a scheduled output pulse.

Apparatus and method for performing spike analysis in a logic simulator

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