High resolution sample clock generator with deglitcher

Claim 2

A digital controlled clock, comprising: (a) means for generating a plurality of phase clock signals having an equally-spaced phase relationship; (b) commutator means for selecting one of the plurality of phase clock signals; and (c) means for removing spikes from the selected phase clock signal.

Claim 3

A digital controlled clock for generating a sample clock signal for use in recovering data from a received signal, the digital controlled clock comprising: (a) a multi-phase clock generator comprising (i) a crystal oscillator that provides a reference clock signal having a preselected frequency; (ii) a multi-stage ring oscillator that provides a plurality of phase clock signals having the preselected frequency and an equally-spaced phase relationship; and (iii) an analog phase locked loop connected to receive the reference clock signal and one of the phase clock signals for locking the frequency of the phase clock signals to the preselected frequency; (b) a phase commutator for selecting one of the phase clock signals comprising (i) a multiplexor that receives the plurality of phase clock signals as inputs and provides the selected phase clock signal as an output based on a select input signal; and (ii) means responsive to a phase advance/retard input signal for generating the select input signal; and (c) a clock deglitcher for removing spikes from the selected phase clock signal to provide the sample clock signal.

Claim 4

A digital controlled clock for generating a sample clock signal for use in recovering data from a received signal, the digital controlled clock comprising: (a) a multi-phase clock generator comprising (i) a crystal oscillator that provides a reference clock signal having a preselected frequency; (ii) a multi-stage ring oscillator that provides a plurality of phase clock signals having the preselected frequency and an equally-spaced phase relationship; and (iii) an analog phase locked loop connected to receive the reference clock signal and one of the phase clock signals for locking the frequency of the phase clock signals to the preselected frequency; (b) a phase commutator for selecting one of the phase clock signals comprising (i) a multiplexor that receives the plurality of phase clock signals as inputs and provides the selected phase clock signal as an output based on a select input signal; and (ii) means responsive to a phase advance/retard input signal for generating the select input signal; and (c) a clock deglitcher for removing spikes from the selected phase clock signal to provide the sample clock signal.

Claim 5

A digital controlled clock as in claim 2 wherein the deglitcher comprises: (a) a first delay stage for delaying the selected phase clock signal by a first preselected amount to provide a first delay stage output; (b) a second delay stage for delaying the first delay stage output by a second preselected amount to provide a second delay stage output; and (c) a NAND gate which receives the first and second delay stage outputs as inputs and provides the sample clock as an output.

Claim 6

A digital controlled clock as in claim 3 wherein the first delay stage comprises a pair of series-connected inverter elements and the second delay stage comprises two pair of series-connected inverter elements, each of the inverter elements of the first and second delay stages being matched to the inverters of the VCO.

Claim 7

A digital controlled clock as in claims 3 and further comprising: (a) a third delay stage for delaying the sample clock signal by the second preselected amount to provide a third delay stage output; and (b) a second NAND gage which receives the sample clock signal and the third delay stage output as inputs and provides a sample clock output having a preselected duty cycle.

Claim 8

A digital controlled clock as in claim 5 wherein the third delay stage comprises two pair of series-connected inverters that are matched to the inverters of the VCO such that the sample clock output has a 50/50 duty cycle.

Claim 9

A digital controlled clock for generating a sample clock signal for use in recovering data from a received signal, the digital controlled clock comprising: (a) a multiphase-clock generator comprising (i) a crystal oscillator that provides a reference clock signal having a preselected frequency; (ii) a voltage controlled oscillator (VCO) comprising a plurality of series-­connected VCO inverters arranged in a ring configuration, the output of each inverter providing one of a plurality of phase clock signals having the preselected frequency and an equally-spaced phased relationship; and (iii) an analog phase locked loop connected to receive the reference clock signal and one of the phase clock signals for generating a control voltage for the VCO such that the frequency of the phase clock signals is locked to the preselected frequency; (b) a phase commutator for selecting one of the phase clock signals comprising (i) multiplexor means for selecting one of the plurality of phase clock signals in response to a control signal; (ii) a state machine responsive to an input signal for providing the control signal; and (iii) storage means for storing the previous state machine input signal and responsive to an advance/retard input code for providing an updated state machine input signal; and (c) deglitcher means for removing spikes from the selected phase clock signal to provide a recovered clock signal.

Claim 10

A digital controlled clock for generating a sample clock signal for use in recovering data from a received signal, the digital controlled clock comprising: (a) a multiphase-clock generator comprising (i) a crystal oscillator that provides a reference clock signal having a preselected frequency; (ii) a voltage controlled oscillator (VCO) comprising a plurality of series-­connected VCO inverters arranged in a ring configuration, the output of each inverter providing one of a plurality of phase clock signals having the preselected frequency and an equally-spaced phased relationship; and (iii) an analog phase locked loop connected to receive the reference clock signal and one of the phase clock signals for generating a control voltage for the VCO such that the frequency of the phase clock signals is locked to the preselected frequency; (b) a phase commutator for selecting one of the phase clock signals comprising (i) multiplexor means for selecting one of the plurality of phase clock signals in response to a control signal; (ii) a state machine responsive to an input signal for providing the control signal; and (iii) storage means for storing the previous state machine input signal and responsive to an advance/retard input code for providing an updated state machine input signal; and (c) deglitcher means for removing spikes from the selected phase clock signal to provide a recovered clock signal.

Claim 11

A digital controlled clock as in claim 7 wherein the deglitcher means comprises: (a) a first delay stage comprising two series-connected inverters for delaying the selected phase clock signal by a first preselected amount to provide a first delay stage output; (b) a second delay stage comprising four series-connected inverters for delaying the first delay stage output by a second preselected amount to provide a second delay stage output; and (c) a NAND gate which receives the first and second delay stage outputs as inputs as provides the sample clock as an output.

Claim 12

A digital controlled clock as in claim 8 wherein each of the inverters comprising the first and second delay stages is matched to the inverters of the VCO.

Claim 13

A digital controlled clock as in claim 9 and further comprising: (a) a third delay stage comprising four inverters, each of which is matched to the inverters comprising the VCO, for delaying the sample clock signal by the second preselected amount to provide a third delay stage output; and (b) a second NAND gate which receives the sample clock signal and the third delay stage output and provides a sample clock output having a 50/50 duty cycle.

Claim 14

A digital controlled clock as in Claim 7 wherein the advance/retard input code to the storage means comprises a two-bit code wherein a first bit enables the phase commutator to make phase jumps among the plurality of clock signals and second bit determines the direction of the phase jump.

Claim 19

A method as in claim 13 wherein the step of removing spikes from the selected phase clock signal comprises: (a) delaying the selected phase clock signal by a first preselected amount to provide a first delay stage output signal; (b) delaying the first stage delay output signal by a second preselected amount to provide a second delay stage output; and (c) providing the first and second delay stage outputs as inputs to a NAND gate which provides the sample clock signal as an output.

Claim 20

A method as in claim 14 and further comprising: (a) delaying the sample clock signal by the second preselected amount to provide a third delay stage output; and (b) providing the sample clock signal and the third delay stage output as inputs to second NAND gate which provides a sample clock output having a preselected duty cycle.

Claim 21

A method as in claim 15 wherein the sample clock output has a 50/50 duty cycle.