Thin film multilayer laminate interconnection board assembly method

Claim 2

A process for assembling a multilayer laminate interconnection board including a pin carrier substrate comprising the steps of: (a) providing a composite layer by forming a predetermined conductor pattern including at least one via and an associated conductive gound plane on a free standing layer of organic dielectric film; (b) laminating by adhesive said composite layer onto the pin carrier substrate, aligning a respective via in said composite layer with an associated via in the substrate; (c) forming a hole through said composite layer and adhesive at the location of a respective via in said layer; (d) depositing metal in the formed hole, and (e) repeating steps a to d for successive composite layers, each composite layer being superposed and aligned on an immediately preceeding layer, whereby a via on a respective layer is electrically connected to a via on an immediately preceeding layer.

Claim 3

A process for assembling a multilayer laminate interconnection board including a pin carrier substrate comprising the steps of: (a) providing a first composite layer by forming a predetermined conductor pattern including at least one via and an associated conductive ground plane on a first free standing layer of organic dielectric film; (b) laminating by adhesive said first composite layer onto the pin carrier substrate, aligning a respective via on said first composite layer with an associated via on the substrate; (c) forming a hole through said first composite layer and adhesive at the location of the respective via in said first composite layer; (d) depositing metal in the formed hole; (e) providing a second composite layer by forming a predetermined conductor pattern including at least one via on an associated conductive ground plane on a second free standing layer of organic dielectric film; (f) laminating by adhesive said second composite layer onto said first composite layer, aligning a respective via on said second composite layer with an associated via on said first composite layer; (g) forming a hole through said second composite layer and adhesive at the location of the respective via in said second composite layer; (h) depositing metal in the formed hole to electrically connect the respective via on said second composite layer to the associated via on said first composite layer; (i) providing a subsequent composite layer by forming a predetermined conductor pattern having at least one via and an associated conductive ground plane on a subsequent free standing layer of organic dielectric film; (j) laminating by adhesive a subsequent composite layer onto a previously laminated composite layer aligning a respective via on said subsequent composite layer with an associated via on the previously laminated composite layer; (k) forming a hole through said subsequent composite layer and adhesive at the location of the respective via on said subsequent composite layer; (l) depositing metal in the formed hole to electrically connect the via on said subsequent composite layer to the via on the previously laminated composite layer, and (m) repeating steps (i) through (1) for each composite layer in the multilayer laminate interconnection board.

Claim 4

A process for assembling a multilayer laminate interconnection board including a pin carrier substrate comprising the steps of: (a) providing a first composite layer by forming a predetermined conductor pattern including at least one via and an associated conductive ground plane on a first free standing layer of organic dielectric film; (b) laminating by adhesive said first composite layer onto the pin carrier substrate, aligning a respective via on said first composite layer with an associated via on the substrate; (c) forming a hole through said first composite layer and adhesive at the location of the respective via in said first composite layer; (d) depositing metal in the formed hole; (e) providing a second composite layer by forming a predetermined conductor pattern including at least one via on an associated conductive ground plane on a second free standing layer of organic dielectric film; (f) laminating by adhesive said second composite layer onto said first composite layer, aligning a respective via on said second composite layer with an associated via on said first composite layer; (g) forming a hole through said second composite layer and adhesive at the location of the respective via in said second composite layer; (h) depositing metal in the formed hole to electrically connect the respective via on said second composite layer to the associated via on said first composite layer; (i) providing a subsequent composite layer by forming a predetermined conductor pattern having at least one via and an associated conductive ground plane on a subsequent free standing layer of organic dielectric film; (j) laminating by adhesive a subsequent composite layer onto a previously laminated composite layer aligning a respective via on said subsequent composite layer with an associated via on the previously laminated composite layer; (k) forming a hole through said subsequent composite layer and adhesive at the location of the respective via on said subsequent composite layer; (l) depositing metal in the formed hole to electrically connect the via on said subsequent composite layer to the via on the previously laminated composite layer, and (m) repeating steps (i) through (1) for each composite layer in the multilayer laminate interconnection board.

Claim 5

A process for assembling a multilayer laminate interconnection board including a pin carrier substrate comprising the steps of: (a) providing a first composite layer by forming a predetermined conductor pattern including at least one via on a first free standing layer of organic dielectric film and an associated conductive ground plane; (b) laminating by adhesive said first composite layer onto the pin carrier substrate, aligning a respective via on said first composite layer with an associated via on the substrate; (c) forming a hole through said first composite layer and adhesive at the location of the respective via on said first composite layer; (d) depositing metal in the formed hole to electrically connect the respective via on said first composite layer to an associated via on the substrate; (e) providing a second composite layer by forming a predetermined conductor pattern including at least one via on a second free standing layer of organic dielectric film and an associated conductive ground plane; (f) laminating by adhesive said second conductive layer onto said first conductive layer of film, aligning a respective via on said second conductive layer with an associated via on said first conductive layer; (g) forming a hole through said second conductive layer and adhesive at the location of the re­spective via on said second conductive layer, and (h) depositing metal in a formed hole to electric­ally connect the respective via on said second conductive layer to the associated via on said first conductive layer.

Claim 6

A process for assembling a multilayer laminate interconnection board including a pin carrier substrate comprising the steps of: (a) providing a first composite layer by forming a predetermined conductor pattern including at least one via on a first free standing layer of organic dielectric film and an associated conductive ground plane; (b) laminating by adhesive said first composite layer onto the pin carrier substrate, aligning a respective via on said first composite layer with an associated via on the substrate; (c) forming a hole through said first composite layer and adhesive at the location of the respective via on said first composite layer; (d) depositing metal in the formed hole to electrically connect the respective via on said first composite layer to an associated via on the substrate; (e) providing a second composite layer by forming a predetermined conductor pattern including at least one via on a second free standing layer of organic dielectric film and an associated conductive ground plane; (f) laminating by adhesive said second conductive layer onto said first conductive layer of film, aligning a respective via on said second conductive layer with an associated via on said first conductive layer; (g) forming a hole through said second conductive layer and adhesive at the location of the re­spective via on said second conductive layer, and (h) depositing metal in a formed hole to electric­ally connect the respective via on said second conductive layer to the associated via on said first conductive layer.

Claim 7

A process of assembling a multilayer laminate interconnection board including a pin carrier substrate comprising the steps of: (a) providing a first composite layer by forming a predetermined conductor pattern including at least one via and an associated conductive ground plane on a free standing layer of organic dielectric film; (b) laminating by adhesive said first composite layer onto the pin carrier substrate, aligning a respective via on said first composite layer with an associated via on the substrate; (c) providing a subsequent composite layer by forming a predetermined conductor pattern having at least one via and an associated conductive ground plane on a subsequent free standing layer of organic dielectric film; (d) laminating by adhesive a subsequent composite layer onto a previously laminated composite layer aligning a respective via on said sub­sequent composite layer with an associated via on the previously laminated composite layer; (e) repeating step (d) for each composite layer in the multilayer laminate interconnection board.

Claim 8

A process of assembling a multilayer laminate interconnection board including a pin carrier substrate comprising the steps of: (a) providing a first composite layer by forming a predetermined conductor pattern including at least one via and an associated conductive ground plane on a free standing layer of organic dielectric film; (b) laminating by adhesive said first composite layer onto the pin carrier substrate, aligning a respective via on said first composite layer with an associated via on the substrate; (c) providing a subsequent composite layer by forming a predetermined conductor pattern having at least one via and an associated conductive ground plane on a subsequent free standing layer of organic dielectric film; (d) laminating by adhesive a subsequent composite layer onto a previously laminated composite layer aligning a respective via on said sub­sequent composite layer with an associated via on the previously laminated composite layer; (e) repeating step (d) for each composite layer in the multilayer laminate interconnection board.

Claim 9

A process for assembling a multilayer laminate interconnection board as set forth in any one of the preceding claims 1 to 4, wherein said organic dielectric film is a polyimide film.

Claim 10

A process for assembling a multilayer laminate interconnection board as set forth in any one of the preceding claims, wherein said conductor pattern and associated conductive ground plane comprise copper.

Claim 11

A process for assembling a multilayer laminate interconnection board as set forth in any one of the preceding claims, wherein said adhesive is a polyimide adhesive.

Claim 12

A process for assembling a multilayer laminate interconnection board as set forth in any one of the preceding claims, wherein said forming a hole is selected from etching, laser ablating and drilling.

Claim 13

A process for assembling a multilayer laminate interconnection board as set forth in claim 1, wherein said depositing metal is selected from evaporation, sputtering and plating.

Claim 14

A multilayer laminate interconnection board including a pin carrier substrate assembled according to the process as set forth in any one of the preceding claims.