Multiple instruction issue computer architecture

Claim 2

In a data processor, an improved instruction processing system that facilitates processing instructions at a rate of more than one instruction per clock, said system comprising: means for fetching a family of n, n being a predetermined integer, sequential instructions in a program; a pipeline, having a series of pipeline stages, including resources for accepting a family of n instructions at each pipeline stage during a single clock, with said accepted family of the type including multiple nonbranching instructions, with one of said nonbranching instructions being a memory reference type of instruction, so that said pipeline can retire a family of instructions and accept a new family of instructions each clock; a decoder, responsive to a fetched family of instructions, for generating a decode result associated with said fetched family of instructions; means, responsive to said decode result, for issuing said fetched family of instructions during one clock; means, responsive to said decode result, for controlling said pipeline to process said fetched family of instructions and to advance said fetched family through said pipeline stages.

Claim 3

The system of claim 1 wherein said pipeline comprises: a decode stage for accessing control signals to execute said family of instructions; a data address generating stage; a fetch operand stage; an arithmetic and logic operations stage; and a writeback/store stage.

Claim 4

The invention of claim 2 wherein said pipeline resources comprise: a multiported register file for storing resulting data from the execution of instructions in the family and for providing operands required to execute instructions in said fetched family when said fetched family is being processed in said fetch operand stage; and means for directly providing given resulting data from the execution of a first instruction as operand data required to execute a second instruction in the family, dependent on said given resulting data, prior to storing said resulting data in said register file operand stage.

Claim 5

In a data processor, an improved instruction processing system that facilitates processing instructions at a rate of more than one instruction per clock, said system comprising: means for fetching a family of n, n being a predetermined integer, sequential instructions in a program; a pipeline, having a series of pipeline stages, including resources for accepting a family of n predetermined selected types of instructions at each pipeline stage during a single clock, with said accepted family including multiple nonbranching instructions, with one of said instructions being a memory reference type of instruction, so that said pipeline can retire a family of instructions and accept a new family of instructions each clock; a decoder, responsive to a fetched family of instructions, for generating a decode result associated with said fetched family of instructions; means, responsive to said decode result, for issuing said fetched family of instructions during one clock only if said fetched family of instructions consists of said predetermined selected types of instructions; means, responsive to said decode result, for controlling said pipeline to process said fetched family of instructions and to advance said family through said pipeline stages.

Claim 6

In a data processor, an improved instruction processing system that facilitates processing instructions at a rate of more than one instruction per clock, said system comprising: means for fetching a family of n, n being a predetermined integer, sequential instructions in a program; a pipeline, having a series of pipeline stages, including resources for accepting a family of n predetermined selected types of instructions at each pipeline stage during a single clock, with said accepted family including multiple nonbranching instructions, with one of said instructions being a memory reference type of instruction, so that said pipeline can retire a family of instructions and accept a new family of instructions each clock; a decoder, responsive to a fetched family of instructions, for generating a decode result associated with said fetched family of instructions; means, responsive to said decode result, for issuing said fetched family of instructions during one clock only if said fetched family of instructions consists of said predetermined selected types of instructions; means, responsive to said decode result, for controlling said pipeline to process said fetched family of instructions and to advance said family through said pipeline stages.

Claim 7

The invention of claim 4 wherein said decoder further comprises: means for determining whether said fetched family of instructions consists only of said predetermined selected types of instructions; and wherein said means for issuing further comprises: means, responsive to said means for determining, for issuing said fetched family in one clock only if said fetched family consists of said predetermined selected types of instructions.

Claim 8

The system of claim 5 wherein said pipeline comprises: a decode stage for accessing control signals to execute said family of instructions; a data address generating stage; a fetch operand stage; an arithmetic and logic operations stage; and a writeback/store stage.

Claim 9

The invention of claim 6 wherein said pipeline resources comprise: a multiported register file for storing resulting data from the execution of instructions in said fetched family and for providing operands required to execute instructions in said family when said fetched family is being processed in said fetch operand stage; and means for directly providing given resulting data from the execution of a first instruction as operand data required to execute a second instruction in the family, dependent on said given resulting data, prior to storing said resulting data in said register file operand stage.

Claim 10

In a computer that includes resources, such as registers, an ALU, and an instruction pipeline for executing the ordered instructions in a program, a system for simultaneously executing a family of consecutive instructions in the program, said system comprising: means for fetching a first family of instructions including multiple non-branching instructions with one of said instructions being a memory load or memory writeback type instruction; a decoder, responsive to said fetched family of instructions, for generating a decode result associated with said family of fetched instructions; means, responsive to said decode result, for issuing all the instructions in said fetched family of instructions during a first clock cycle; and means, responsive to said decode result, for fetching a second family of instructions that may be issued during a second clock cycle immediately following said first clock cycle.

Claim 11

In a computer that includes resources, such as registers, an ALU, and an instruction pipeline for executing the ordered instructions in a program, a system for simultaneously executing a family of consecutive instructions in the program, said system comprising: means for fetching a first family of instructions including multiple non-branching instructions with one of said instructions being a memory load or memory writeback type instruction; a decoder, responsive to said fetched family of instructions, for generating a decode result associated with said family of fetched instructions; means, responsive to said decode result, for issuing all the instructions in said fetched family of instructions during a first clock cycle; and means, responsive to said decode result, for fetching a second family of instructions that may be issued during a second clock cycle immediately following said first clock cycle.

Claim 12

The system of claim 8 wherein one of said instructions is a load immediate instruction.

Claim 13

The system of claim 8 wherein one of said instructions is an ALU type of instruction.

Claim 14

In a computer system of the type that includes resources, such as registers and an ALU, and an instruction pipeline for sequentially executing the ordered instructions in a program, a subsystem for simultaneously executing a family of consecutive instructions in the program, said subsystem comprising: means for fetching the family of instructions; a decoder, responsive to said fetched instructions, for generating an entry point field associated with each fetched instruction, with each entry point field including a status field indicating the resources required to execute the fetched instruction associated with the entry point field; means, responsive to said entry point status fields associated with said fetched instructions, for generating an indication that said fetched instructions may be simultaneously executed only if said status fields indicate that the execution of said fetched instructions will not cause a resource conflict; and means, responsive to said indication and said entry point fields, for creating a family execution entry point field for accessing a microcode routine for simultaneously executing the family of instructions.

Claim 15

In a computer system of the type that includes resources, such as registers and an ALU, and an instruction pipeline for sequentially executing the ordered instructions in a program, a subsystem for simultaneously executing a family of consecutive instructions in the program, said subsystem comprising: means for fetching the family of instructions; a decoder, responsive to said fetched instructions, for generating an entry point field associated with each fetched instruction, with each entry point field including a status field indicating the resources required to execute the fetched instruction associated with the entry point field; means, responsive to said entry point status fields associated with said fetched instructions, for generating an indication that said fetched instructions may be simultaneously executed only if said status fields indicate that the execution of said fetched instructions will not cause a resource conflict; and means, responsive to said indication and said entry point fields, for creating a family execution entry point field for accessing a microcode routine for simultaneously executing the family of instructions.

Claim 16

The invention of claim 11 wherein the instructions are stored in an addressable instruction store and the instruction pipeline includes a prefetch address generation unit that generates the address of a following instruction to be fetched from the instruction store while a present address is being decoded, said subsystem further comprising: means, responsive to said indication, for setting the prefetch address to a value that causes a following family of instructions to be prefetched.

Claim 17

In a computer system of the type that includes resources, such as registers and an ALU, and an instruction pipeline for sequentially executing the ordered instructions in a program, a subsystem for simultaneously executing a family of consecutive instructions in the program, said subsystem comprising: means for fetching the family of instructions; a decoder, responsive to said fetched instructions, for generating a decode result associated with each fetched instruction, with each decode result including a status field indicating the resources required to execute the fetched instruction associated with the decode result; means, responsive to said status fields associated with said fetched instructions, for creating an indication that said fetched instructions may be simultaneously executed only if said status fields indicate that the execution of said fetched instructions will not cause a resource conflict; and means, responsive to said indication and said decoding result, for generating a family execution decode result; and means, responsive to said family execution decode result, for concurrently issuing the family of instructions.

Claim 18

In a computer system of the type that includes resources, such as registers and an ALU, and an instruction pipeline for sequentially executing the ordered instructions in a program, a subsystem for simultaneously executing a family of consecutive instructions in the program, said subsystem comprising: means for fetching the family of instructions; a decoder, responsive to said fetched instructions, for generating a decode result associated with each fetched instruction, with each decode result including a status field indicating the resources required to execute the fetched instruction associated with the decode result; means, responsive to said status fields associated with said fetched instructions, for creating an indication that said fetched instructions may be simultaneously executed only if said status fields indicate that the execution of said fetched instructions will not cause a resource conflict; and means, responsive to said indication and said decoding result, for generating a family execution decode result; and means, responsive to said family execution decode result, for concurrently issuing the family of instructions.

Claim 19

The subsystem of claim 13 wherein said means for simultaneously executing further comprises: means for concurrently executing the family of instructions despite dependencies between instructions in the family of instructions.

Claim 20

The subsystem of claim 14 further comprising: a multiported register file for storing resulting data from the execution of instructions in the family and for providing operands required to execute instructions in the family; and means for directly providing given resulting data from the execution of a first instruction as operand data required to execute a second instruction in the family, dependent on said given resulting data, prior to storing said resulting data in said register file.

Claim 21

In a computer that includes resources such as registers and an ALU and executes a program of sequential instructions selected from a predetermined instruction set, a system for simultaneously executing selected pairs of instructions included in a first subset of the instruction set where, during sequential execution, the second instruction in the selected pair depends on the first instruction in the sense that the execution of the second instruction depends on a result of the execution of the first instruction, said system comprising: means for fetching a given pair of sequential instructions in the program; decoding means for generating a decoding result for each instruction in the fetched pair; means, responsive to said decoding results, for indicating whether said given pair is one of the selected pairs that may be simultaneously executed; a data unit, responsive to said means for indicating and adapted to receive said decoding result, for creating a pair identification if said given fetched pair is one of the selected pairs; and an execution unit, responsive to said identification, for simultaneously executing the given selected pair by eliminating the dependency present during the sequential execution of the given pair.

Claim 22

In a computer that includes resources such as registers and an ALU and executes a program of sequential instructions selected from a predetermined instruction set, a system for simultaneously executing selected pairs of instructions included in a first subset of the instruction set where, during sequential execution, the second instruction in the selected pair depends on the first instruction in the sense that the execution of the second instruction depends on a result of the execution of the first instruction, said system comprising: means for fetching a given pair of sequential instructions in the program; decoding means for generating a decoding result for each instruction in the fetched pair; means, responsive to said decoding results, for indicating whether said given pair is one of the selected pairs that may be simultaneously executed; a data unit, responsive to said means for indicating and adapted to receive said decoding result, for creating a pair identification if said given fetched pair is one of the selected pairs; and an execution unit, responsive to said identification, for simultaneously executing the given selected pair by eliminating the dependency present during the sequential execution of the given pair.

Claim 23

The invention of claim 16 wherein said decoding results include fields of data indicating whether each instruction is included in said first subset of selected instructions and which computer resources are required to execute the instruction.

Claim 24

The invention of claim 16 wherein said means for indicating is adapted to receive said data fields and indicates that said given pair is one of said selected pairs only if said data fields indicate that both fetched instructions are included in said first subset and that no resource conflict results from the simultaneous execution of the fetched pair.

Claim 25

In a computer that executes a program of sequential instructions selected from a predetermined instruction set, a method for simultaneously executing selected pairs of instructions where, during sequential execution, the second instruction in the pair depends on the first instruction in the sense that the execution of the second instruction depends on a result of the execution of the first instruction, said method comprising: fetching a given pair of sequential instruction in the program; generating a decoding result for each instruction in the fetched pair; in response to said decoding results, indicating whether said given pair is one of the selected pairs that may be simultaneously executed; in response to said indication and said decoding result, creating a pair identification if said given fetched pair is one of the selected pairs; and in response to said identification, simultaneously executing the given selected pair by eliminating the dependency present during the sequential execution of the given pair.

Claim 26

In a computer that executes a program of sequential instructions selected from a predetermined instruction set, a method for simultaneously executing selected pairs of instructions where, during sequential execution, the second instruction in the pair depends on the first instruction in the sense that the execution of the second instruction depends on a result of the execution of the first instruction, said method comprising: fetching a given pair of sequential instruction in the program; generating a decoding result for each instruction in the fetched pair; in response to said decoding results, indicating whether said given pair is one of the selected pairs that may be simultaneously executed; in response to said indication and said decoding result, creating a pair identification if said given fetched pair is one of the selected pairs; and in response to said identification, simultaneously executing the given selected pair by eliminating the dependency present during the sequential execution of the given pair.