Paired instruction processor precise exception handling mechanism

Claim 2

In a data processor of the type that issues a family of instructions during a single clock and includes a pipeline for executing instructions in several stages, the pipeline including a first given stage for calculating memory references and performing ALU operations and a second given stage for writing data, and with the data processor including exception handling procedures for handling exceptions associated with the execution of a single instruction, an exception handling procedure for handling an exception that occurs during the execution of a given family of instructions issued during a single clock comprising the steps of: generating an indication, during the first given pipeline stage, that an exception, associated with an instruction in the given family, has occurred during the execution of the given family; testing for the presence of said indication to detect the occurrence of an exception; inhibiting, during the second given pipeline stage, the data write associated with the execution of the given family; flushing instructions from all the stages of the pipeline; and reissuing a first instruction in the given family to be executed singly so that the existing exception handling procedure may be utilized to handle the exception if the exception was associated with said first instruction.

Claim 3

The method of claim 1 wherein said step of testing includes the step of: determining whether an overflow bit has been set to indicate an arithmetic overflow exception associated with an ALU instruction.

Claim 4

The method of claim 1 wherein said step of testing includes the step of: determining whether a page fault bit has been set to indicate a page fault exception associated with an memory reference instruction.

Claim 5

The procedure of claim 1 wherein said step of reissuing further comprises the steps of: storing the address of each instruction in the family; singly accessing said first instruction in the family with said stored address of said first instruction; and reissuing said first instruction.

Claim 6

In a data processor of the type that issues a family of instructions during a single clock and includes a pipeline for executing instructions in several stages, the pipeline including a first given stage for calculating memory references and performing ALU operations and a second given stage for writing data, and with the data processor including exception handling procedures for handling exceptions associated with the execution of a single instruction, an exception handling system for handling an exception that occurs during the execution of a given family of instructions issued during a single clock comprising: means for generating an indication, during the first given pipeline stage, that an exception, associated with an instruction in the given family, has occurred during the execution of the given family; means for testing for the presence of said indication to detect the occurrence of an exception; means for inhibiting, during the second given pipeline stage, the data write associated with the execution of the given family; means for flushing instructions from all the stages of the pipeline; and means for reissuing a first instruction in the given family to be executed singly so that the existing exception handling procedure may be utilized to handle the exception if the exception was associated with said first instruction.

Claim 7

In a data processor of the type that issues a family of instructions during a single clock and includes a pipeline for executing instructions in several stages, the pipeline including a first given stage for calculating memory references and performing ALU operations and a second given stage for writing data, and with the data processor including exception handling procedures for handling exceptions associated with the execution of a single instruction, an exception handling system for handling an exception that occurs during the execution of a given family of instructions issued during a single clock comprising: means for generating an indication, during the first given pipeline stage, that an exception, associated with an instruction in the given family, has occurred during the execution of the given family; means for testing for the presence of said indication to detect the occurrence of an exception; means for inhibiting, during the second given pipeline stage, the data write associated with the execution of the given family; means for flushing instructions from all the stages of the pipeline; and means for reissuing a first instruction in the given family to be executed singly so that the existing exception handling procedure may be utilized to handle the exception if the exception was associated with said first instruction.

Claim 8

The system of claim 5 wherein said means for testing includes: means for testing whether an overflow bit has been set to indicate an arithmetic overflow exception associated with an ALU instruction.

Claim 9

The system of claim 5 wherein said means for testing includes: means for testing whether a page fault bit has been set to indicate a page fault exception associated with a memory reference instruction.

Claim 10

The system of claim 5 wherein said means for reissuing further comprises: means for storing the address of each instruction in the family; means for singly accessing said first instruction in the family with said stored address of said first instruction; and means for reissuing said first instruction.