Patent EP0399207A2 successfully refreshed from Google Patents.
EP0399207A2
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EP
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Test selection system
Assignee: International Business Machines Corp
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Filing: 1990-04-18
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Granted: —
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Expires: 2010-04-18
Abstract
Abstract A test selection system is provided which includes a semiconductor substrate (S) having a pin (AX) connected thereto and an integrated circuit (M) disposed on the substrate (S) and connected to the pin (AX) having an operating voltage within a given voltage range. A latch conditioning circuit (12) having an input responsive to a voltage of a given magnitude has an output (NB) connected to a latch (14), and a voltage control circuit (10) operable at a voltage without the given voltage range selectively applies a control voltage of the given magnitude to the input of the latch conditioning circuit (12). A voltage without the given voltage range is applied to the pin (AX) during a first interval of time to produce the control voltage for establishing a test mode and a voltage within the given voltage range is applied to the pin (AX) during a second interval of time to establish a normal operating mode for the integrated circuit (M).
Inventors
- 👤 Jeffrey H. Dreibelbis
- 👤 John A. Gabric
- 👤 Erik L. Hedberg
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 17:49
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
176 words
A test selection system comprising a semiconductor substrate, a pin (AX) connected to said semiconductor substrate (S), integrated circuit means (M) connected to said pin (AX) operable at a first operating voltage within a given voltage range, control voltage circuit means (10) connected to said pin (AX) having an output (NA) producing a control voltage operable at a second voltage without said given voltage range, means for applying said second voltage to said pin (AX) during a first period of time, a latch (14) having an input and an output (NC), a latch conditioning circuit (12) having an output (NB) connected to the input of said latch (14) and an input responsive to the control voltage from the output (NA) of said control voltage circuit means (10), a test enable terminal (NE), a buffer circuit (16) having an input connected to the output (NC) of said latch (14) and an output connected to said test enable terminal (NE), and means for applying said first operating voltage to said pin (AX) during a second period of time.
Claim 2
Dependent Claim
176 words
A test selection system comprising a semiconductor substrate, a pin (AX) connected to said semiconductor substrate (S), integrated circuit means (M) connected to said pin (AX) operable at a first operating voltage within a given voltage range, control voltage circuit means (10) connected to said pin (AX) having an output (NA) producing a control voltage operable at a second voltage without said given voltage range, means for applying said second voltage to said pin (AX) during a first period of time, a latch (14) having an input and an output (NC), a latch conditioning circuit (12) having an output (NB) connected to the input of said latch (14) and an input responsive to the control voltage from the output (NA) of said control voltage circuit means (10), a test enable terminal (NE), a buffer circuit (16) having an input connected to the output (NC) of said latch (14) and an output connected to said test enable terminal (NE), and means for applying said first operating voltage to said pin (AX) during a second period of time.
Claim 3
Dependent Claim
27 words
A test selection system as set forth in claim 1 wherein said control voltage circuit means (10) includes a plurality of serially arranged diodes (N1 to N5).
Claim 4
Dependent Claim
39 words
A test selection system as set forth in claim 2 wherein said control voltage circuit means (10) further includes a resistor (R) connected between said plurality of serially arranged diodes (N1 to N5) and a point of reference potential.
Claim 5
Dependent Claim
38 words
A test selection system as set forth in anyone of the claims 1 to 3 wherein said control voltage circuit means further includes an isolating device (P1) interposed between said pin (AX) and said point of reference potential.
Claim 6
Dependent Claim
25 words
A test selection system as set forth in claim 4 further including means for activating said isolating device (P1) after said control voltage is produced.
Claim 7
Dependent Claim
36 words
A test selection system as set forth in claim 5 wherein said isolating means includes a transistor (P1) and said activating means includes means for applying said first voltage to a control electrode of said transistor.
Claim 8
Dependent Claim
44 words
A test selection system as set forth in claim 6 wherein said transistor (P1) is a P-channel field effect transistor and wherein each diode of said plurality of serially arranged diodes (N1 to N5) is an N-channel field effect transistor arranged as a diode.
Claim 9
Dependent Claim
56 words
A test selection system as set forth in anyone of the claims 1 to 7 wherein said latch conditioning circuit (12) includes first and second serially connected transistors (P2, N6) having its output (NB) at the common point between said transistors and its input at a control electrode of one of said first and second transistors.
Claim 10
Dependent Claim
100 words
A test selection system as set forth in claim 8 wherein said first transistor (P2) is a P-channel field effect transistor connected between the output (NB) of said latch conditioning circuit (12) and a first point of reference potential and having a control electrode connected to the output (NB) of said latch conditioning circuit, and said second transistor (N6) is an N-channel field effect transistor connected between a second point of reference potential and the output (NB) of the latch conditioning circuit (12) and having a control electrode connected to the output (NA) of said control voltage circuit means (10).
Claim 11
Dependent Claim
63 words
A test selection system as set forth in anyone of the claims 1 to 9 wherein said latch (14) includes first and second inverters each having an input and an output with the output of said first inverter being connected to the input of said second inverter and the output of the second inverter being connected to the input of said first inverter.
Claim 12
Dependent Claim
31 words
A test selection system as set forth in claim 10 wherein each of said inverters includes a P-channel field effect transistor (P3, P4) and an N-channel field effect transistor (N7, N8).
Claim 13
Dependent Claim
29 words
A test selection system as set forth in anyone of the claims 1 to 11 further including a capacitor (C) connected to the output (NC) of said latch (14).
Claim 14
Dependent Claim
89 words
A test selection system as set forth in anyone of the claims 1 to 12 wherein said buffer circuit (16) includes first and second inverters (P5, N4; P6, N10) each having an input and an output, with the input of said first inverter (P5, N9) being connected to the output (NC) of said latch (14) and the output (ND) of the first inverter being connected to the input of said second inverter (P6, N10), and the output of said second inverter being connected to said test enable terminal (NE).
Claim 15
Dependent Claim
66 words
A test selection system as set forth in anyone of the claims 1 to 13 further including a logic circuit (20) having first and second inputs (NE, A1) and an output (T1), the first input of said logic circuit being connected to said test enable terminal (NE) and the second input (A1) of said logic circuit (20) being connected to a source of address input signals.
Claim 16
Dependent Claim
19 words
A test selection system as set forth in claim 14 wherein said logic circuit (20) is an AND circuit.
Claim 17
Dependent Claim
59 words
A test selection system as set forth in claim 15 wherein said AND circuit comprises a NAND circuit (P7, P8, N11, N12) including the first and second inputs (NE, A1) of said logic circuit and an inverter (P9, N13), with said inverter being interposed between the output of said NAND circuit and the output (T1) of said logic circuit.
Claim 18
Dependent Claim
50 words
A test selection system as set forth in anyone of the claims 1 to 16 further including a second pin (AY) connected to said semiconductor substrate (S), and a disabling circuit (10′) connected to said second pin (AY) and having an output (NA′) coupled to said latch conditioning circuit (12).
Claim 19
Dependent Claim
40 words
A test selection system as set forth in claim 17 wherein said disabling circuit (10′) includes a plurality of serially arranged diodes (N1′to N5′) and a resistor (R′) connected between said second pin (AY) and a point of reference potential.
References Cited (Backward Citations)
No citation records indexed.
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