Negative feedback circuit to control the duty cycle of a logic system clock

Abstract

Abstract A circuit for controlling the duty cycle of a high frequency logic system clock using negative feedback. A high-level buffer (18) used to drive the system clock bus receives the output of a crystal oscillator (40). The buffer output (50) is sampled by an integrator circuit which produces a voltage level corresponding to the duty cycle of the clock, and this voltage level is compared to a reference voltage using an operational amplifier (60). The op-amp output (70) is applied to the buffer input (75) as negative feedback to alter the bias level at the buffer input (75) in a way as to vary the point in the rising and falling transitions of the crystal oscillator (40) where the threshold of the buffer (48) is crossed. A circuit (52,54) monitors the clock signal output of a high-level buffer (48), and determines whether the duty cycle of the crystal oscillator (40) which drives the output buffer (48) should be increased or decreased. A corresponding DC bias to the input of the output buffer (48) causes the crystal oscillator (40) output to reach threshold levels of the output buffer (48) at different times during each clock pulse, thus adjusting the duty cycle of the buffer output (50). An RC integrator (52,54) is used to monitor the buffer output, and the output of this integrator is compared with a reference voltage in an operational amplifier (60). The output of the operational amplifier (60) biases the input (75) to the output buffer (48) to a level corresponding to a need to increase or decrease the duty cycle of the buffer output clock signal.

Inventors

• 👤 Joseph P. Miller

Bibliographic Details