Patent EP0398628A2 successfully refreshed from Google Patents.
EP0398628A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1990-05-15
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Granted: —
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Expires: 2010-05-15
Abstract
Abstract A semiconductor memory device (1) comprising a supporting board (3), a plurality of semiconductor IC chips (4) arranged on the supporting board, in which interconnection is provided between the semiconductor chips and between the semiconductor chip and the supporting board. On the portion of the upper surface including the active area, of the semiconductor chip such as a memory IC chip bonding electrodes are arranged so as to extend substantially toward the confronting side. A plurality of such a memory IC chip are arranged on a single supporting board and the adjacent memory IC chips are directly connected by means of a bonding wire (6) or the like. Accordingly, this semiconductor memory device allows predetermined semiconductor IC chips to be mounted more densely and more compactly without requiring arrangement of conductive patterns (5) for connecting the semiconductor IC chips on a circuit board.
Inventors
- 👤 Shigeru C/O Intellectual Yatabe
- 👤 Akinori C/O Intellectual Hongu
- 👤 Hiroshi C/O Intellectual Yamada
- 👤 Masayuki C/O Intellectual Saito
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 13:38
CPC Classifications
H; H10; H10W; H10W72/00; H10W44/00; H10W44/601; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/65; H10W90/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/541; H10W72/5445; H10W72/90; H10W72/931; H10W72/932; H10W90/701; H10W90/751; H10W90/753; H10W90/754
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
91 words
A semiconductor memory device comprising: a supporting board; a plurality of semiconductor IC chips arranged on said supporting board; interconnection provided between said semiconductor IC chips and between said semiconductor IC chip and said supporting board; said semiconductor IC chip having at least two electrode pads for receiving information from a single signal line or sending information to a single signal line and means for directly interconnecting between said electrode pads corresponding with and adjacent to each other on each of said semiconductor IC chips that are adjacent to each other.
Claim 2
Dependent Claim
91 words
A semiconductor memory device comprising: a supporting board; a plurality of semiconductor IC chips arranged on said supporting board; interconnection provided between said semiconductor IC chips and between said semiconductor IC chip and said supporting board; said semiconductor IC chip having at least two electrode pads for receiving information from a single signal line or sending information to a single signal line and means for directly interconnecting between said electrode pads corresponding with and adjacent to each other on each of said semiconductor IC chips that are adjacent to each other.
Claim 3
Dependent Claim
35 words
A semiconductor memory device as claimed in claim 1, wherein bonding electrodes for said semiconductor IC chip is provided on a portion of the upper surface of said semiconductor IC chip including the active area.
Claim 4
Dependent Claim
93 words
A semiconductor memory device as claimed in claim 2, wherein said semiconductor IC chip with said bonding electrodes arranged comprises a passivation film formed on a portion of the upper surface of said semiconductor IC chip excluding bonding pads, a first insulating layer formed on said passivation film, interconnection patterns formed on said insulating layer and connected to said bonding pads, a second insulating layer formed on said interconnection patterns excluding a portion of said interconnection patterns, and conductive patterns farmed on said second insulating layer and electrically connected to said interconnection patterns.
Claim 5
Dependent Claim
31 words
A semiconductor memory device as claimed in claim 3, wherein said conductive patterns are arranged so that respective patterns extend in parallel toward the confronting side of said semiconductor IC chip.
Claim 6
Dependent Claim
105 words
A semiconductor memory device comprising: a supporting board; a plurality of semiconductor IC chips arranged on said supporting board; interconnection provided between said semiconductor IC chips and between said semiconductor IC chip and said supporting board; bonding electrodes being provided in parallel so as to extend substantially toward the corresponding side on a part of the upper surface including the active area of said semiconductor IC chip; at least one of said bonding electrodes intersecting another bonding electrode; means for directly interconnecting between said bonding electrodes adjacent to each other on each of said semiconductor IC chips that are adjacent to each other being provided.
Claim 7
Dependent Claim
105 words
A semiconductor memory device comprising: a supporting board; a plurality of semiconductor IC chips arranged on said supporting board; interconnection provided between said semiconductor IC chips and between said semiconductor IC chip and said supporting board; bonding electrodes being provided in parallel so as to extend substantially toward the corresponding side on a part of the upper surface including the active area of said semiconductor IC chip; at least one of said bonding electrodes intersecting another bonding electrode; means for directly interconnecting between said bonding electrodes adjacent to each other on each of said semiconductor IC chips that are adjacent to each other being provided.
Claim 8
Dependent Claim
112 words
A semiconductor memory device comprising: a supporting board; a plurality of semiconductor IC chips arranged on said supporting board; interconnection provided between said semiconductor IC chips and between said semiconductor IC chip and said supporting board; bonding electrodes being provided in parallel so as to extend substantially toward the corresponding side on a part of the upper surface of said semiconductor IC chip excluding the active area; means for directly interconnecting between said bonding electrodes adjacent to each other on each of said semiconductor IC chips that are adjacent to each other being provided; at least one of said direct interconnection means for interconnecting said bonding electrodes intersecting other direct interconnection means.
Claim 9
Dependent Claim
112 words
A semiconductor memory device comprising: a supporting board; a plurality of semiconductor IC chips arranged on said supporting board; interconnection provided between said semiconductor IC chips and between said semiconductor IC chip and said supporting board; bonding electrodes being provided in parallel so as to extend substantially toward the corresponding side on a part of the upper surface of said semiconductor IC chip excluding the active area; means for directly interconnecting between said bonding electrodes adjacent to each other on each of said semiconductor IC chips that are adjacent to each other being provided; at least one of said direct interconnection means for interconnecting said bonding electrodes intersecting other direct interconnection means.
Claim 10
Dependent Claim
19 words
A semiconductor memory device as claimed in claim 6, wherein said means for interconnecting said bonding electrodes is insulated.
Claim 11
Dependent Claim
29 words
A semiconductor memory device as claimed in claim 1, 2, 3, 4, 5, 6 or 7, wherein said means for interconnecting said bonding electrodes is wired by wire bonding.
Claim 12
Dependent Claim
30 words
A semiconductor memory device as claimed in claim 1, 2, 3, 4, 5, 6 or 7, wherein said means for interconnecting said bonding electrodes is wired by tape automated bonding.
Claim 13
Dependent Claim
51 words
A semiconductor memory device comprising: a supporting board; a plurality of semiconductor IC chips arranged on said supporting board; interconnection provided between said semiconductor IC chips and between said semiconductor IC chip and said supporting board; and at least one capacitor formed on the upper face of said semiconductor IC chip.
Claim 14
Dependent Claim
51 words
A semiconductor memory device comprising: a supporting board; a plurality of semiconductor IC chips arranged on said supporting board; interconnection provided between said semiconductor IC chips and between said semiconductor IC chip and said supporting board; and at least one capacitor formed on the upper face of said semiconductor IC chip.
Claim 15
Dependent Claim
83 words
A semiconductor memory device comprising: a supporting board; a plurality of semiconductor IC chips arranged on said supporting board; said semiconductor IC chip having at least two electrode pads for receiving information from a single signal line or sending information to a single signal line; said electrode pads adjacent to each other on each of said semiconductor IC chips that are adjacent to each other being directly wired; and at least one capacitor formed on the upper face of said semiconductor IC chip.
Claim 16
Dependent Claim
83 words
A semiconductor memory device comprising: a supporting board; a plurality of semiconductor IC chips arranged on said supporting board; said semiconductor IC chip having at least two electrode pads for receiving information from a single signal line or sending information to a single signal line; said electrode pads adjacent to each other on each of said semiconductor IC chips that are adjacent to each other being directly wired; and at least one capacitor formed on the upper face of said semiconductor IC chip.
Claim 17
Dependent Claim
84 words
A semiconductor memory device as claimed in claim 10 or 11, wherein said capacitor comprises: an insulating layer arranged on the active area of the upper surface of said semiconductor IC chip; a first conductive pattern formed on said insulating layer and connected to at least an electrode pad; a dielectric layer formed on said first conductive pattern; and a second conductive pattern formed on said dielectric layer, sharing an area that overlap that of the first conductive pattern and connected to other electrodes.
Claim 18
Dependent Claim
19 words
A semiconductor memory device as claimed in claim 12, wherein said dielectric layer is essentially consisted of barium titanate.
References Cited (Backward Citations)
No citation records indexed.
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