Patent EP0398568A2 successfully refreshed from Google Patents.
EP0398568A2
Expired / Lapsed
EP
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Multiplier circuit
Assignee: AT&T Inc
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Filing: 1990-05-04
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Granted: —
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Expires: 2010-05-04
Abstract
Abstract In a multiplier for binary numbers represented in two's complement notation, the need to perform sign-bit extension in order to combine the partial products is avoided by representing the value represented by the sign bits of all the partial products as a two's complement number in its own right. The bits of that number, rather than the original sign bits, are then used in the partial product addition. Since (as with all two's complement numbers) all the bits of the sign-bit-value word are guaranteed to have positive significance (except for the left-most one), the digits of the partial products can then be directly added without the need for sign bit extension.
Inventors
- 👤 Sailesh Krishna Rao
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 16:35
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/533; G06F7/5334; G06F7/5336; G06F7/5338; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3852; G06F7/499; G06F7/49994
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
69 words
A method for adding a plurality of two's complement numbers, the sign bits of at least ones of said numbers having respective different positional significances, said method characterized by the steps of generating a two's complement number whose value is equal to the combined values represented by the sign bits of said plurality of numbers, and combining said generated number with the non-sign bits of said plurality of numbers.
Claim 2
Independent Claim
69 words
A method for adding a plurality of two's complement numbers, the sign bits of at least ones of said numbers having respective different positional significances, said method characterized by the steps of generating a two's complement number whose value is equal to the combined values represented by the sign bits of said plurality of numbers, and combining said generated number with the non-sign bits of said plurality of numbers.
Claim 3
Dependent Claim
150 words
A circuit for multiplying two numbers, said circuit characterized by means responsive to said two numbers for generating a plurality of partial products in two's complement form, and means responsive to said partial products for combining a plurality of modified two's complement numbers each of which is the same as a respective associated one of said partial products except that in each of said modified numbers, two bits replace the sign bit of the associated partial product, the highest-order one of said two bits being 1 and the second-highest-order one of said two bits being a) in the case of the one of said partial products having the sign bit of lowest significance, the sum of the inverse of the sign bit of that partial product and 1 and b) in the case of each other partial product, the inverse of the sign bit of said each other partial product.
Claim 4
Dependent Claim
150 words
A circuit for multiplying two numbers, said circuit characterized by means responsive to said two numbers for generating a plurality of partial products in two's complement form, and means responsive to said partial products for combining a plurality of modified two's complement numbers each of which is the same as a respective associated one of said partial products except that in each of said modified numbers, two bits replace the sign bit of the associated partial product, the highest-order one of said two bits being 1 and the second-highest-order one of said two bits being a) in the case of the one of said partial products having the sign bit of lowest significance, the sum of the inverse of the sign bit of that partial product and 1 and b) in the case of each other partial product, the inverse of the sign bit of said each other partial product.
References Cited (Backward Citations)
No citation records indexed.
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