Patent EP0398468A2 successfully refreshed from Google Patents.
EP0398468A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Dielectrically isolated substrate and semiconductor device using the same
Assignee: Toshiba Corp
•
Filing: 1990-02-28
•
Granted: —
•
Expires: 2010-02-28
Abstract
Abstract A dielectric isolation substrate comprises a first semiconductor wafer (101), a second semiconductor wafer (102) bonded on the first semiconductor wafer (101) with a first insulating layer (103) interposed therebetween, a semiconductor layer 104) formed on the second semiconductor wafer (102), a first groove (105) formed in the semiconductor layer (104) and the second semiconductor wafer (102) so as to reach the first insulating layer (103), thereby isolating the semiconductor layer (104) and the second semiconductor wafer (102), and a second insulating layer (106) formed on the side face of the first groove (105) or embedded in the first groove (105). In this dielectric isolation substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove (105).
Inventors
- 👤 Akio C/O Intellectual Property Division Nakagawa
- 👤 Kazuyoshi C/O Intellectual Property Div Furukawa
- 👤 Tsuneo C/O Intellectual Property Division Ogura
- 👤 Katsujiro C/O Intellectual Property Div. Tanzawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 17:47
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/031; H10D; H10D12/00; H10D12/411; H10D12/421; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/835; H10D86/00; H10D86/201; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W10/061; H10W10/10; H10W10/181; H10W10/30; H10P90/1914; H10W10/011; H10W10/014; H10W10/041; H10W10/17; H10W10/40
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
99 words
A dielectric isolation substrate comprising: a first semiconductor wafer (101); a second semiconductor wafer (102) bonded on said first semiconductor wafer with a first insulating layer (103) interposed therebetween; a semiconductor layer (104) formed on the second semiconductor wafer (102); a first groove (105) formed in said semiconductor layer (104) and said second semiconductor wafer (102) so as to reach said insulating layer (103), thereby isolating the semiconductor layer (104) and the second semiconductor wafer (102); and a second insulating layer (106) formed on the side surface of the first groove (105) or embedded in the first groove (105).
Claim 2
Dependent Claim
99 words
A dielectric isolation substrate comprising: a first semiconductor wafer (101); a second semiconductor wafer (102) bonded on said first semiconductor wafer with a first insulating layer (103) interposed therebetween; a semiconductor layer (104) formed on the second semiconductor wafer (102); a first groove (105) formed in said semiconductor layer (104) and said second semiconductor wafer (102) so as to reach said insulating layer (103), thereby isolating the semiconductor layer (104) and the second semiconductor wafer (102); and a second insulating layer (106) formed on the side surface of the first groove (105) or embedded in the first groove (105).
Claim 3
Dependent Claim
28 words
The substrate according to claim 1, characterized in that said semiconductor layer (104) has a conductivity type opposite to the conductivity type of the second semiconductor wafer (102).
Claim 4
Dependent Claim
82 words
The substrate according to claim 2, characterized in that a semiconductor region (109), having the same conductivity type as the second semiconductor wafer (102) and having an impurity concentration higher than that of the second semiconductor wafer (102), is formed in those regions of the semiconductor layer (104) and the second semiconductor wafer (102) isolated by the first insulating layer (103) and the second insulating layer (106), which are adjacent to the first insulating layer (103) and the second insulating layer (106).
Claim 5
Dependent Claim
24 words
The substrate according to claim 1, characterized in that said semiconductor layer (104) has the same conductivity type as the second semiconductor wafer (102).
Claim 6
Dependent Claim
38 words
The substrate according to claim 1, characterized in that said second insulating layer (106) is an oxide film formed on the side face of the first groove (105), and polycrystalline silicon is filled in the first groove (105).
Claim 7
Dependent Claim
24 words
The substrate according to claim 1, characterized in that said second insulating layer (106) is formed of resin filled in the first groove (105).
Claim 8
Dependent Claim
49 words
The substrate according to claim 1, characterized by further comprising a second groove 133) formed in said semiconductor layer (104) and isolating said semiconductor layer (104), and a third insulating layer (134) formed on the side face of the second groove 133) or filled in the second groove (133).
Claim 9
Dependent Claim
38 words
The substrate according to claim 7, characterized in that said third insulating layer (134) is an oxide film formed on the side face of the second groove (133), and polycrystalline silicon is filled in the second groove (133).
Claim 10
Dependent Claim
24 words
The substrate according to claim 7, characterized in that said third insulating layer (134) is formed of resin filled in the second groove (133).
Claim 11
Dependent Claim
53 words
The substrate according to claim 1, characterized in that said second insulating layer (106) is an oxide film formed on the side face of the first groove (105), polycrystalline silicon is filled in the first groove (105), and said third insulating layer (134) is formed of resin filled in the second groove (133).
Claim 12
Dependent Claim
119 words
A semiconductor device comprising: a first semiconductor wafer (101); a second semiconductor wafer (102) bonded on said first semiconductor wafer (101) with a first insulating layer (103) interposed therebetween; a semiconductor layer (104) formed on the second semiconductor wafer (102); a groove (105) formed in said semiconductor layer (104) and said second semiconductor wafer (102) so as to reach said insulating layer (103), thereby isolating the semiconductor layer (104) and the second semiconductor wafer (102); a second insulating layer (106) formed on the side face of the groove (105) or embedded in the first groove (105); a high breakdown voltage element formed in said semiconductor layer (104); and a low breakdown voltage element formed in said semiconductor layer (104).
Claim 13
Dependent Claim
119 words
A semiconductor device comprising: a first semiconductor wafer (101); a second semiconductor wafer (102) bonded on said first semiconductor wafer (101) with a first insulating layer (103) interposed therebetween; a semiconductor layer (104) formed on the second semiconductor wafer (102); a groove (105) formed in said semiconductor layer (104) and said second semiconductor wafer (102) so as to reach said insulating layer (103), thereby isolating the semiconductor layer (104) and the second semiconductor wafer (102); a second insulating layer (106) formed on the side face of the groove (105) or embedded in the first groove (105); a high breakdown voltage element formed in said semiconductor layer (104); and a low breakdown voltage element formed in said semiconductor layer (104).
Claim 14
Dependent Claim
50 words
The semiconductor device according to claim 11, characterized in that said high breakdown voltage element and said low breakdown voltage element are formed in the same region of the semiconductor layer (104) isolated by said second insulating layer (106), and these elements are isolated from each other by a pn-junction.
Claim 15
Dependent Claim
32 words
The semiconductor device according to claim 11, characterized in that said high breakdown voltage element and said low breakdown voltage element are isolated from each other by said second insulating layer (106).
Claim 16
Dependent Claim
28 words
The semiconductor device according to claim 11, characterized in that said low breakdown voltage element is isolated from the second semiconductor wafer (102) by means of a pn-junction.
Claim 17
Dependent Claim
65 words
The semiconductor device according to claim 11, characterized in that a high breakdown voltage element and a plurality of low breakdown voltage elements are formed in said semiconductor layer (104), the high breakdown voltage element is isolated from the low breakdown voltage elements by said second insulating layer (106), and the low breakdown voltage elements are isolated from each other by means of a pn-junction.
Claim 18
Dependent Claim
112 words
The semiconductor device according to claim 11, characterized by further comprising a second groove (133) formed in the semiconductor layer (104) and isolating the semiconductor layer (104) into a plurality of regions, and a third insulating layer (134) formed on the side face of the second groove (133) or filled in the second groove (133), wherein a high breakdown voltage element and a plurality of low breakdown voltage elements are formed in said semiconductor layer (104), the high breakdown voltage element is isolated from the low breakdown voltage elements by said second insulating layer (106), and the low breakdown voltage elements are isolated from each other by the third insulating layer (134).
Claim 19
Independent Claim
137 words
A method of manufacturing a dielectric isolation substrate comprising the steps of: bonding first and second semiconductor wafers(101, 102), the surface of at least one of which is provided with a first insulating layer (103), such that the first insulating layer (103) is interposed between the first and second semiconductor wafers (101, 102); forming an epitaxial grown layer (104) on the second semiconductor wafer (102); forming a first groove (105) in the epitaxially grown layer (104) and the second semiconductor wafer (102) so as to reach the first insulating layer (103), thereby isolating the epitaxial grown layer (104) and the second semiconductor wafer (102) into a plurality of regions; and forming a second insulating layer (106) on the side face of said first groove (105) or embedding the second insulating layer (106) in the first groove (105).
Claim 20
Independent Claim
137 words
A method of manufacturing a dielectric isolation substrate comprising the steps of: bonding first and second semiconductor wafers(101, 102), the surface of at least one of which is provided with a first insulating layer (103), such that the first insulating layer (103) is interposed between the first and second semiconductor wafers (101, 102); forming an epitaxial grown layer (104) on the second semiconductor wafer (102); forming a first groove (105) in the epitaxially grown layer (104) and the second semiconductor wafer (102) so as to reach the first insulating layer (103), thereby isolating the epitaxial grown layer (104) and the second semiconductor wafer (102) into a plurality of regions; and forming a second insulating layer (106) on the side face of said first groove (105) or embedding the second insulating layer (106) in the first groove (105).
Claim 21
Dependent Claim
60 words
The method according to claim 17, characterized by further comprising the steps of: forming a second groove (133) in the epitaxially grown layer (104) to isolate it into a plurality of regions; and forming a third insulating layer (134) on the side face of the second groove (133), or embedding the third insulating (134) layer in the second groove (133).
Claim 22
Dependent Claim
53 words
The method according to claim 17, characterized in that said second insulating layer (134) is an oxide film formed on the side face of the first groove (133), polycrystalline silicon is filled in the first groove (133), and the third insulating layer (134) is formed of resin filled in the second groove (133).
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.