Patent EP0398249A2 successfully refreshed from Google Patents.
EP0398249A2
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1990-05-15
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Granted: —
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Expires: 2010-05-15
Abstract
Abstract In one-transistor·one-capacitor type dynamic memory cell, a cell capacitor with a reduced junction leakage current comprises a MOS capacitor (C₁) which is provided between a semiconductor substrate (1) and a charge storage electrode (11) disposed on a side wall of a trench through a first insulating film (9), and a stacked capacitor (C₂) which is provided between the charge storage electrode (11) and a capacitor plate electrode (13) formed on a second insulating film (12) covering the entire surface of the charge storage electrode (11). The equivalent silicon dioxide thickness of the first insulating film (9) is thicker than that of the second insulating film (12), and the storage capacitance of the cell capacitor is rendered by a sum of the capacitance of the MOS capacitor (C₁) and the capacitance of the stacked capacitor (C₂) because these capacitors are electrically connected in parallel with each other.
Inventors
- 👤 Jumpei C/O Intellectual Property Div. Kumagai
- 👤 Shizuo C/O Intellectual Property Div. Sawada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 19:46
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0156
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
130 words
In a semiconductor memory device including dynamic memory cells each being comprised of one transistor (TR) and one cell capacitor, said transistor being provided in an opposite conductivity type well region (3) formed in one conductivity type semiconductor substrate, said cell capacitor provided in a trench formed in said semiconductor substrate through said well region (3), characterized by comprising: a first insulating film (9) formed on an inner wall of said trench; a charge storage electrode (11) disposed on said first insulating film (9); a second insulating film (12) provided on said charge storage electrode (11), an equivalent silicon dioxide thickness of said first insulating film (9) being thicker than that of said second insulating film (12); and a capacitor plate electrode (13) disposed on said second insulating film (12).
Claim 2
Dependent Claim
130 words
In a semiconductor memory device including dynamic memory cells each being comprised of one transistor (TR) and one cell capacitor, said transistor being provided in an opposite conductivity type well region (3) formed in one conductivity type semiconductor substrate, said cell capacitor provided in a trench formed in said semiconductor substrate through said well region (3), characterized by comprising: a first insulating film (9) formed on an inner wall of said trench; a charge storage electrode (11) disposed on said first insulating film (9); a second insulating film (12) provided on said charge storage electrode (11), an equivalent silicon dioxide thickness of said first insulating film (9) being thicker than that of said second insulating film (12); and a capacitor plate electrode (13) disposed on said second insulating film (12).
Claim 3
Dependent Claim
58 words
The semiconductor memory device according to claim 1, characterized in that said cell capacitor includes a MOS capacitor (C₁) provided by said semiconductor substrate, said first insulating film (9) and said charge storage electrode (11), and a stacked capacitor (C₂) rendered by said charge storage electrode (11), said second insulating film (12) and said capacitor plate electrode (13).
Claim 4
Dependent Claim
32 words
The semiconductor memory device according to claim 1, characterized in that said first insulating film (9) is composed of a material selected from an SiO₂, an Si₃N₄, a Ta₂O₃, a Y₂O₃, etc.
Claim 5
Dependent Claim
33 words
The semiconductor memory device according to claim 1, characterized in that said first insulating film (9) is comprised of a composite film composed of an SiO₂, and Si₃N₄, a Ta₂O₃ and a Y₂O₃.
Claim 6
Dependent Claim
32 words
The semiconductor memory device according to claim 1, characterized in that said second insulating film (12) is composed of a material selected from an SiO₂, an Si₃N₄, a Ta₂O₃, a Y₂O₃, etc.
Claim 7
Dependent Claim
33 words
The semiconductor memory device according to claim 1, characterized in that said second insulating film (12) is comprised of a composite film composed of an SiO₂, an Si₃N₄, a Ta₂O₃ and a Y₂O₃.
Claim 8
Dependent Claim
27 words
The semiconductor memory device according to claim 2, characterized in that the capacitance of said MOS capacitor (C₁) is lower than that of said stacked capacitor (C₂).
Claim 9
Dependent Claim
32 words
The semiconductor memory device according to claim 2, characterized in that said charge storage electrode (11) is electrically connected to a source or drain region (17 or 18) of said transistor (TR).
Claim 10
Dependent Claim
28 words
The semiconductor memory device according to claim 2, characterized in that said MOS capacitor (C₁) and said stacked capacitor (C₂) are equivalently connected in parallel with each other.
Claim 11
Dependent Claim
51 words
The semiconductor memory device according to claim 1, characterized in that said one conductivity type semiconductor substrate comprises one conductivity type epitaxial layer (2) with a comparatively low impurity concentration grown on one conductivity type semiconductor substrate (1) having an impurity concentration of 1 × 10¹⁸ to 1 × 10²¹ cm⁻³.
Claim 12
Dependent Claim
39 words
The semiconductor memory device according to claim 1, characterized in that said one conductivity type semiconductor substrate comprises only one semiconductor substrate of one conductivity type having an impurity concentration of 1 × 10¹⁵ to 1 × 10¹⁸ cm⁻³.
References Cited (Backward Citations)
No citation records indexed.
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