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EP0398247A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semidonductor device and method of manufacturing the same

Assignee: Toshiba Corp
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Filing: 1990-05-15
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Granted: —
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Expires: 2010-05-15
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Abstract

Abstract At least part of a low impurity concentration col­lector region (4, 6) which lies between the emitter (30) and collector regions (4, 6) of a bipolar transistor in a Bi-CMOS device is formed to have a low impurity concentration. Therefore, a high emitter-collector withstanding voltage can be obtained. Further, at least part of the low impurity concentration collector region (4, 6) which lies between the base region (24) and an opposite conductivity type region (5) is formed to have a high impurity concentration. Therefore, the punch-­through withstanding voltage of a parasitic transistor formed of the base (24), collector (6) and, opposite conductivity type region (5) can be enhanced, and, at the same time, the collector resistance can be reduced.

Inventors

  • 👤 Hiroshi C/O Intellectual Property Div. Momose
  • 👤 Yukari C/O Intellectual Property Div. Unno

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-08 02:59
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 173 words
A semiconductor device comprising: a semiconductor substrate (1); an emitter region (30) of a first conductivity type formed on said semiconductor substrate (1); a base region (24) of a second conductivity type formed to surround said emitter region (30); a low impurity concentration collector region (4, 6) of the first conductivity type formed to surround said base region (24); a high impurity concentration collector region (2) of the first conductivity type formed under said low impurity concentration collector region (4, 6); and a well region (5) of the second conductivity type formed in contact with said low impurity concentration collector region (4, 6); characterized in that at least part of said low impurity concentration collector region (4, 6) which lies between said emitter region (30) and said high impurity concentration collector region (2) is formed to have an impurity concentration lower than that of at least part of said low impurity concentration collector region (4, 6) which lies between said base region (24) and said well region (5) of the second conductivity type.
Claim 2
Dependent Claim 173 words
A semiconductor device comprising: a semiconductor substrate (1); an emitter region (30) of a first conductivity type formed on said semiconductor substrate (1); a base region (24) of a second conductivity type formed to surround said emitter region (30); a low impurity concentration collector region (4, 6) of the first conductivity type formed to surround said base region (24); a high impurity concentration collector region (2) of the first conductivity type formed under said low impurity concentration collector region (4, 6); and a well region (5) of the second conductivity type formed in contact with said low impurity concentration collector region (4, 6); characterized in that at least part of said low impurity concentration collector region (4, 6) which lies between said emitter region (30) and said high impurity concentration collector region (2) is formed to have an impurity concentration lower than that of at least part of said low impurity concentration collector region (4, 6) which lies between said base region (24) and said well region (5) of the second conductivity type.
Claim 3
Dependent Claim 98 words
A semiconductor device according to claim 1, characterized by further comprising a first conductivity type region (6) formed on said semiconductor substrate (1); source (17) and drain (18) regions of the second conductivity type separately formed on said first con­ductivity type region; and an electrode (13) formed on said first conductivity type region (6) which lies between said source (17) and drain (18) regions; characterized in that the high impurity concentration portion (30) formed in said low impurity concentration collector region (4, 6) and said first conductivity type region (6) are formed to have the same impurity concentration.
Claim 4
Dependent Claim 61 words
A semiconductor device according to claim 1, characterized in that the impurity concentration of a portion (4) of said low impurity concentration collector region (4, 6) which lies directly below said emitter region (30) is lower than that of a portion (6) of said low impurity concentration collector region (4, 6) which does not lie directly below said emitter region (30).
Claim 5
Dependent Claim 98 words
A semiconductor device according to claim 3, characterized by further comprising a first conductivity type region (6) formed on said semiconductor substrate (1); source (17) and drain (18) regions of the second conductivity type separately formed on said first con­ductivity type region; and an electrode (13) formed on said first conductivity type region (5) which lies between said source (21) and drain (22) regions; characterized in that the high impurity concentra­tion portion (30) formed in said low impurity concentra­tion collector region (4, 6) and said first conductivity type region (6) are formed to have the same impurity concentration.
Claim 6
Dependent Claim 59 words
A semiconductor device according to claim 1, characterized in that the impurity concentration of a portion (4) of said low impurity concentration collector 3u region (4 6) which lies directly below said base region (24) is lower than that of a portion of said low impu­rity concentration collector region which does not lie directly below said base region (24).
Claim 7
Dependent Claim 98 words
A semiconductor device according to claim 5, characterized by further comprising a first conductivity type region (6) formed on said semiconductor substrate (1); source (17) and drain (18) regions of the second conductivity type separately formed on said first con­ductivity type region; and an electrode (13) formed on said first conductivity type region (6) which lies between said source (17) and drain (18) regions; characterized in that the high impurity concentra­tion portion (30) formed in said low impurity concentra­tion collector region (4, 6) and said first conductivity type region (6) are formed to have the same impurity concentration.
Claim 8
Dependent Claim 62 words
A semiconductor device according to claim 1, characterized in that the impurity concentration of the surface area (40) of a portion of said low impurity concentration collector region (4, 6) which lies between said base region (24) and said second conductivity type region (5) is higher than that of the remaining portion (4) of said low impurity concentration collector region (4, 6).
Claim 9
Dependent Claim 106 words
A semiconductor device according to claim 7, characterized by further comprising a first conductivity type region (40) formed on said semiconductor substrate (1); source (17) and drain (18) regions of the second conductivity type separately formed on said first con­ductivity type region (6); an electrode (13) formed on said first conductivity type region which lies between said source (17) and drain (18) regions; and device-isolation insulating film (7); characterized in that the high impurity concentra­tion portion (6) formed in said low impurity concentra­tion collector region (4, 6) and ion-injected region preventing said field region (7) from being inverted are formed to have the same impurity concentration.
Claim 10
Independent Claim 283 words
A method of manufacturing a semiconductor device, comprising the steps of: forming at least two first buried layers (2) having a high impurity concentration on selected surfaces in a second MOS transistor-forming region and a bipolar transistor-forming region of said semiconductor substrate (1), respectively, and forming a second buried layer (3) having a high impurity concentration in a first MOS transistor-forming region of said semiconduc­tor substrate (1); forming an epitaxial layer (4) of a first conduc­tivity type on the entire surfaces of said semiconductor substrate (1); forming a well region (5) of a second conductivity type in said first MOS transistor-forming region, said well region (5) having an impurity concentration higher than that of said epitaxial layer (4); forming simultaneously at least two regions (40, 8) of said first conductivity type in that portion of said epitaxial layer (4) which is located above said second MOS transistor-forming region and ion-injected regions (8) in which said device-isolation insulating film (7) is to be formed, said ion-injected regions preventing said field region from being inverted, and that portion of said epitaxial layer (4) which is located above said bipolar transistor-forming region and other than that portion located below a base-forming portion (40), respectively; forming device-isolation insulating film (7) on selected surfaces of the resultant structure; forming a first MOS transistor in said well region (5) of the second conductivity type formed in said first MOS transistor-forming region, and a second MOS transis­tor in said well region (6) of the first conductivity type formed in said second MOS transistor-forming region; and forming a bipolar transistor in said epitaxial layer (4) and said well region (6) of the first conduc­tivity type formed in said bipolar transistor-forming region.
Claim 11
Independent Claim 283 words
A method of manufacturing a semiconductor device, comprising the steps of: forming at least two first buried layers (2) having a high impurity concentration on selected surfaces in a second MOS transistor-forming region and a bipolar transistor-forming region of said semiconductor substrate (1), respectively, and forming a second buried layer (3) having a high impurity concentration in a first MOS transistor-forming region of said semiconduc­tor substrate (1); forming an epitaxial layer (4) of a first conduc­tivity type on the entire surfaces of said semiconductor substrate (1); forming a well region (5) of a second conductivity type in said first MOS transistor-forming region, said well region (5) having an impurity concentration higher than that of said epitaxial layer (4); forming simultaneously at least two regions (40, 8) of said first conductivity type in that portion of said epitaxial layer (4) which is located above said second MOS transistor-forming region and ion-injected regions (8) in which said device-isolation insulating film (7) is to be formed, said ion-injected regions preventing said field region from being inverted, and that portion of said epitaxial layer (4) which is located above said bipolar transistor-forming region and other than that portion located below a base-forming portion (40), respectively; forming device-isolation insulating film (7) on selected surfaces of the resultant structure; forming a first MOS transistor in said well region (5) of the second conductivity type formed in said first MOS transistor-forming region, and a second MOS transis­tor in said well region (6) of the first conductivity type formed in said second MOS transistor-forming region; and forming a bipolar transistor in said epitaxial layer (4) and said well region (6) of the first conduc­tivity type formed in said bipolar transistor-forming region.
Claim 12
Dependent Claim 72 words
A method according to claim 9, characterized in that said step of forming the well region (6) of the first conductivity type in that portion of said epitaxial layer (4) which is located above said bipolar transistor-forming region and other than that portion located below an emitter-forming portion is to form the well region (6) of the first conductivity type, in con­tact with a base region (24) of the bipolar transistor-­forming region.
Claim 13
Dependent Claim 73 words
A method according to claim 9, characterized in that said step of forming the well region (6) of the first conductivity type in that portion of said epi­taxial layer (4) which is located above said bipolar transistor-forming region and other than that portion located below an emitter-forming portion is to form the well region (106) of the first conductivity type, not in contact with the base region (24) of the bipolar transistor-forming region.
Claim 14
Dependent Claim 43 words
A method according to claim 9, characterized by further comprising the step of forming ion-injected regions (8) for preventing field inversion, in those portions of said first and second MOS transistor-forming regions in which said device-isolation insulating films (7) is to be formed.
Claim 15
Independent Claim 231 words
A method of manufacturing a semiconductor device, characterized by comprising the steps of: forming at least two first buried layers (2) having a high impurity concentration on selected surfaces in a second MOS transistor-forming region and a bipolar transistor-forming region of said semiconductor substrate (1) respectively and forming a second buried layer (3) having a high impurity concentration in a first MOS transistor-forming region of said semiconduc­tor substrate (1); forming an epitaxial layer (4) of a first conduc­tivity type on the entire surfaces of said semiconductor substrate (1); forming a well region (5) of a second conductivity type in said first MOS transistor-forming region, said well region (5) having an impurity concentration higher than that of said epitaxial layer (4); forming a field region (40) of the first conductiv­ity type in the surface of said epitaxial layer (4) which surrounds a base region (24) of said bipolar transistor-forming region; forming device-isolation insulating films (7) on selected surfaces of the resultant structure; forming a first MOS transistor in said well region (5) of the second conductivity type formed in said first MOS transistor-forming region, and a second MOS transis­tor in said well region (6) of the first conductivity type formed in said second MOS transistor-forming region; and forming a bipolar transistor in said epitaxial layer (4) and said well region (6) of the first conduc­tivity type formed in said bipolar transistor-forming region.
Claim 16
Independent Claim 231 words
A method of manufacturing a semiconductor device, characterized by comprising the steps of: forming at least two first buried layers (2) having a high impurity concentration on selected surfaces in a second MOS transistor-forming region and a bipolar transistor-forming region of said semiconductor substrate (1) respectively and forming a second buried layer (3) having a high impurity concentration in a first MOS transistor-forming region of said semiconduc­tor substrate (1); forming an epitaxial layer (4) of a first conduc­tivity type on the entire surfaces of said semiconductor substrate (1); forming a well region (5) of a second conductivity type in said first MOS transistor-forming region, said well region (5) having an impurity concentration higher than that of said epitaxial layer (4); forming a field region (40) of the first conductiv­ity type in the surface of said epitaxial layer (4) which surrounds a base region (24) of said bipolar transistor-forming region; forming device-isolation insulating films (7) on selected surfaces of the resultant structure; forming a first MOS transistor in said well region (5) of the second conductivity type formed in said first MOS transistor-forming region, and a second MOS transis­tor in said well region (6) of the first conductivity type formed in said second MOS transistor-forming region; and forming a bipolar transistor in said epitaxial layer (4) and said well region (6) of the first conduc­tivity type formed in said bipolar transistor-forming region.

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