Patent EP0398191A2 successfully refreshed from Google Patents.
EP0398191A2
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EP
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Quadruple word, multiplexed, paged mode and cache memory
Assignee: Compaq Computer Corp
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Filing: 1990-05-11
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Granted: —
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Expires: 2010-05-11
Abstract
Abstract A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.
Inventors
- 👤 Roy E. Thoma, Iii
- 👤 Joseph P. Miller
- 👤 Bill Skelton
- 👤 Mark Taylor
- 👤 Randy M. Bonella
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 22:47
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0877; G06F12/0886
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
213 words
A computer system, comprising: a processor organized to transfer data n bits wide and providing m bits of addressing; an address bus coupled to said processor to allow transfer of address values; a first data bus coupled to said processor to allow transfer of data values; cache memory coupled to said first data bus and organized as n bits wide; a cache memory controller adapted to be coupled to said address lines so that said cache memory controller utilizes an n bit line size, said cache memory controller being coupled to said cache memory and coupled to said address lines to produce a 2n bit line size; main memory organized as 2n bits wide; a second data bus coupling said cache memory to said main memory, said second data bus being n bits wide; means coupled to said main memory for providing a selected n bits of said 2n bits of said main memory to said second data bus; and means for controlling the transfer of data from said main memory to said cache memory after said cache memory controller determines that a read miss has occurred, said read miss controlling means being coupled to said cache memory controller and to said means for providing selected n bits to said second data bus.
Claim 2
Dependent Claim
213 words
A computer system, comprising: a processor organized to transfer data n bits wide and providing m bits of addressing; an address bus coupled to said processor to allow transfer of address values; a first data bus coupled to said processor to allow transfer of data values; cache memory coupled to said first data bus and organized as n bits wide; a cache memory controller adapted to be coupled to said address lines so that said cache memory controller utilizes an n bit line size, said cache memory controller being coupled to said cache memory and coupled to said address lines to produce a 2n bit line size; main memory organized as 2n bits wide; a second data bus coupling said cache memory to said main memory, said second data bus being n bits wide; means coupled to said main memory for providing a selected n bits of said 2n bits of said main memory to said second data bus; and means for controlling the transfer of data from said main memory to said cache memory after said cache memory controller determines that a read miss has occurred, said read miss controlling means being coupled to said cache memory controller and to said means for providing selected n bits to said second data bus.
Claim 3
Dependent Claim
32 words
The computer system of claim 1, wherein said read miss controlling means includes means for controlling the transfer of data from said main memory at times other than after a read miss.
Claim 4
Dependent Claim
31 words
The computer system of claim 2, wherein said read miss controlling means includes means for indicating when the next address can be presented to said main memory for all memory cycles.
Claim 5
Dependent Claim
32 words
The computer system of claim 2, wherein said read miss controlling means includes means for indicating that said main memory is ready to complete the data transfer cycle for all memory cycles.
Claim 6
Dependent Claim
31 words
The computer system of claim 4, wherein said read miss controlling means includes means for indicating when the next address can be presented to said main memory for all memory cycles.
Claim 7
Dependent Claim
67 words
The computer system of claim 5, wherein said cache memory controller is coupled to said read miss controlling means and responds based on said next address and ready indications, and wherein said read miss controlling means includes means for preventing transfer of said next address and ready indications to said cache memory controller on the transfer of the first n bits of data to said cache memory.
Claim 8
Dependent Claim
32 words
The computer system of claim 1, further comprising: means for disabling said cache memory controller; and means for disabling said read miss controlling means responsive to said cache memory controller being disabled.
Claim 9
Dependent Claim
15 words
The computer system of claim 1, wherein said main memory includes page mode memory devices.
Claim 10
Dependent Claim
24 words
The computer system of claim 8, wherein said read miss controlling means includes means for operating said page mode memory devices in page mode.
Claim 11
Dependent Claim
35 words
The computer system of claim 1, wherein said read miss controlling means includes means for holding address information provided to said main memory valid while said 2n bits are being transferred to said cache memory.
Claim 12
Dependent Claim
34 words
The computer system of claim 1, wherein said read miss controlling means includes means for selecting the proper n bits of said cache memory of said 2n bits recognized by said cache memory controller.
Claim 13
Dependent Claim
10 words
The computer system of claim 1, wherein n is 32.
References Cited (Backward Citations)
No citation records indexed.
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