Patent EP0397408A1 successfully refreshed from Google Patents.
EP0397408A1
Expired / Lapsed
EP
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Reference voltage generator
Assignee: Advanced Micro Devices Inc
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Filing: 1990-05-04
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Granted: —
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Expires: 2010-05-04
Abstract
Abstract A CMOS circuit which can act as a current regulator for a variety of general MOS circuits. The circuit has current-biasing network connected to the source electrode of a first transistor. The drain electrode of the first transistor is connected to an input terminal of a current mirror arrangment. The output terminal of the current mirror is connected to the drain electrode of a first diode-configured transistor. The source electrode of the first diode-configured transistor is connected to a second diode-configured transistor. By connecting output terminals at various nodes of the circuit, the current of a variety of MOS circuits may be regulated by the current-biasing network.
Inventors
- 👤 William C. Plants
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 14:43
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; G05F3/26; G05F3/262
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
225 words
An MOS integrated circuit connected between a first voltage supply and a second voltage supply for generating a reference voltage, comprising a current-biasing device having first and second electrodes, said first electrode connected to said second voltage supply, said device having a first current through said second electrode; a first transistor having first and second source/drain electrodes and a gate electrode, said first source/drain electrode connected to said second electrode of said current-biasing device; a current mirror connected to said first voltage supply having first and second electrodes, said first electrode connected to said second electrode of said first transistor, said second terminal having a second current therethrough mirroring the current through said first electrode; a second transistor in a diode configuraton, said second transistor having first and second source/drain electrodes and a gate electrode, said second source/drain electrode connected to said second electrode of said current mirror, said gate electrode connected to said gate electrode of said first transistor; and a third transistor in a diode configuraton, said third transistor having a first and second source/drain electrodes, said second source/drain electrode connected to a first source/drain electrode of said second transistor, a first source/drain electrode connected to said second voltage supply; whereby the voltage at said first source/drain electrode of said first transistor is fixed at substantially the threshold voltage of said first transistor.
Claim 2
Dependent Claim
225 words
An MOS integrated circuit connected between a first voltage supply and a second voltage supply for generating a reference voltage, comprising a current-biasing device having first and second electrodes, said first electrode connected to said second voltage supply, said device having a first current through said second electrode; a first transistor having first and second source/drain electrodes and a gate electrode, said first source/drain electrode connected to said second electrode of said current-biasing device; a current mirror connected to said first voltage supply having first and second electrodes, said first electrode connected to said second electrode of said first transistor, said second terminal having a second current therethrough mirroring the current through said first electrode; a second transistor in a diode configuraton, said second transistor having first and second source/drain electrodes and a gate electrode, said second source/drain electrode connected to said second electrode of said current mirror, said gate electrode connected to said gate electrode of said first transistor; and a third transistor in a diode configuraton, said third transistor having a first and second source/drain electrodes, said second source/drain electrode connected to a first source/drain electrode of said second transistor, a first source/drain electrode connected to said second voltage supply; whereby the voltage at said first source/drain electrode of said first transistor is fixed at substantially the threshold voltage of said first transistor.
Claim 3
Dependent Claim
29 words
The integrated circuit as in claim 1 wherein the device parameters are such that β₁ equals β₂ where β i = ½ µ0C O X(W/L) for the ith transistor.
Claim 4
Dependent Claim
34 words
The integrated circuit as in claim 2 wherein the channel width over channel length ratio of said second transistor is approximately four times the channel width over channel length ratio of said first transistor.
Claim 5
Dependent Claim
93 words
The integrated circuit as in claim 1 wherein said current mirror comprises a fourth transistor in diode-connected configuration having first and second source/drain electrodes and a gate electrode, said first source/drain electrode connected to said first voltage supply and said second/drain electrode comprising said first current mirror electrode; and a fifth transistor having first and second source/drain electrodes and a gate electrode, said first source/drain electrode connected to said first voltage supply, said gate electrode connected to said fourth transistor gate electrode, and said second source/drain electrode comprising said second current mirror electrode.
Claim 6
Dependent Claim
30 words
The integrated circuit as in claim 4 wherein said first, second, and third transistors are of one polarity type and said fifth and sixth transistors are of another polarity type.
Claim 7
Dependent Claim
25 words
The integrated circuit as in claim 5 wherein transistors of one polarity type are NMOS transistors and transistors of another polarity type are PMOS transistors.
Claim 8
Dependent Claim
14 words
The integrated circuit as in claim 1 wherein said current-biasing device comprises a resistor.
Claim 9
Dependent Claim
32 words
The integrated circuit as in claim 1 wherein said current-biasing device comprises sixth transistor operating in the linear mode, whereby the current through said first transistor is substantially independent of processing variations.
Claim 10
Dependent Claim
89 words
The integrated circuit as in claim 8 further comprising an output terminal connected to said gate electrode of said first transistor, said output terminal for connection to an electrical circuit comprising a seventh transistor having first and second source/drain electrodes and a gate electrode, and a current source having first and second electrodes, said first electrode connected to said second voltage supply and said second electrode connected to said first source/drain electrode of said seventh transistor, whereby the current through said electrical circuit is substantially independent of processing variations.
Claim 11
Dependent Claim
40 words
The integrated circuit as in claim 2 further comprising a current source, said current source connected between said second source/drain electrode of said first transistor and said second voltage supply, whereby a non-conducting state in said integrated circuit is prevented.
Claim 12
Dependent Claim
212 words
An MOS integrated circuit for generating a reference voltage between a first supply voltage and a second supply voltage, comprising first, second and third transistors connected in series between said first supply voltage and said second supply voltage, said first transistor having a first source/drain electrode of said first transistor coupled to said first supply voltage and having a gate electrode connected to a second source/drain electrode, said third transistor having a first source/drain electrode coupled to said second supply voltage and having a gate electrode coupled to said predetermined such that said third transistor operates in the linear region; fourth, fifth and sixth transistors connected in series between said first supply voltage and said second supply voltage, said fourth transistor having a first source/drain electrode coupled to said first supply voltage and a gate electrode connected to said first transistor gate electrode, said sixth transistor having a first source/drain electrode coupled to said second supply voltage and a gate electrode connected to a second source/drain electrode, said fifth transistor having a gate electrode connected to said second transistor gate electrode and to said second source/drain electrode of said fourth transistor; an output terminal connected to said fifth transistor gate electrode; whereby said output terminal voltage remains relatively independent of processing variations.
Claim 13
Dependent Claim
212 words
An MOS integrated circuit for generating a reference voltage between a first supply voltage and a second supply voltage, comprising first, second and third transistors connected in series between said first supply voltage and said second supply voltage, said first transistor having a first source/drain electrode of said first transistor coupled to said first supply voltage and having a gate electrode connected to a second source/drain electrode, said third transistor having a first source/drain electrode coupled to said second supply voltage and having a gate electrode coupled to said predetermined such that said third transistor operates in the linear region; fourth, fifth and sixth transistors connected in series between said first supply voltage and said second supply voltage, said fourth transistor having a first source/drain electrode coupled to said first supply voltage and a gate electrode connected to said first transistor gate electrode, said sixth transistor having a first source/drain electrode coupled to said second supply voltage and a gate electrode connected to a second source/drain electrode, said fifth transistor having a gate electrode connected to said second transistor gate electrode and to said second source/drain electrode of said fourth transistor; an output terminal connected to said fifth transistor gate electrode; whereby said output terminal voltage remains relatively independent of processing variations.
Claim 14
Dependent Claim
18 words
The MOS integrated circuit as in claim 11 wherein said predetermined voltage is substantially said first supply voltage.
Claim 15
Dependent Claim
32 words
The MOS integrated circuit as in claim 12 wherein said first and fourth transistors are a first polarity type and said second, third, fifth and sixth transistors are a second polarity type.
Claim 16
Dependent Claim
22 words
The MOS integrated circuit as in claim 13 wherein said first polarity type is PMOS and said second polarity type is NMOS.
Claim 17
Dependent Claim
38 words
The MOS integrated circuit as in claim 14 wherein the device parameters of said first and fourth transistors are predetermined such that the current through said first transistor is substantially equal to the current through said fourth transistor.
Claim 18
Dependent Claim
35 words
The MOS integrated circuit as in claim 15 wherein the device parameters of said second and fifth transistors are approximately equal so that V T , the threshold voltage, of both transistors are substantially equal.
Claim 19
Dependent Claim
35 words
The MOS integrated circuit as in claim 16 wherein the channel width over channel length ratio of said fifth transistor is approximately four times the channel width over channel length ratio of said second transistor.
Claim 20
Dependent Claim
52 words
The MOS integrated circuit as in claim 17 wherein the device parameters of said fifth and sixth transistors are such that V GS , the gate-source voltage, of said fifth and sixth transistors are substantially equal, whereby V DS , the source-drain voltage, of said third transistor, is substantially V T .
References Cited (Backward Citations)
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