Power delivery circuit with current sensing

Claim 2

A current detection circuit in combination with a current controlling device in a power delivery circuit for supplying load current to a load, the current controlling device being multicellular, with a major current-carrying cellular portion and a minor current-carrying cellular portion, a first main current terminal for connection to a source of power, a gate terminal for receiving a control signal, a second main current terminal connecting the major current-carrying cellular portion, a first auxiliary terminal connected at one end to the minor current-carrying cellular portion so as to provide a current generally proportional to the main device current, and a second auxiliary terminal connected at one end to the major current-carrying cellular portion, and wherein the current detection circuit comprises: first and second branches each for connection at one end to a respective one of said first and said second auxiliary terminals and having means for connection in common at the other end to a reference potential in the power delivery circuit; said first branch including a first series-connected semiconductor device; said second branch including a second series-connected semiconductor device; said first semiconductor device operating in a transimpedance mode and being controlled by a bias signal; said second semiconductor device being cross-connected with said first semiconductor device to provide the respective said bias signal thereto; said first branch further including impedance means connected in series circuit therewith for providing a voltage approximately proportional to the main device current at a node at one end of said impedance means; and wherein said second semiconductor is connected in said second branch in a manner providing a bias signal for controlling said first semiconductor so as to result in said voltage at said node being proportional to the main device current within a relatively small tolerance range across a relatively broad operating range.

Claim 3

The combination of claim 1 wherein said power delivery circuit is connectable to a power supply having a predetermined nominal voltage; said relatively small tolerance range is within about ±3% of the actual main device current; and said relatively broad operating range includes variations in the supply voltage of at least ±25% of said nominal supply voltage, variations between 100 and 500 in the gains (β) of said first and second semiconductors and variations in temperature of ±60°C from an ambient of about 25°C.

Claim 4

The combination of claim 1 or 2 wherein said first and second semiconductors are first and second bipolar transistors respectively and being cross-connected by having their bases connected in common.

Claim 5

The combination of claim 3 wherein said first and said second bipolar transistors are PNP transistors.

Claim 6

The combination of claim 3 or 4 wherein said first and said second bipolar transistors are formed of matched silicon.

Claim 7

The combination of any of claims 3 to 5 wherein the base and the collector of said second bipolar transistor are shorted to one another.

Claim 8

The combination of any of claims 1 to 6 wherein said second branch further includes other impedance means connected in series circuit with said second semiconductor.

Claim 9

The combination of any of claims 1 to 7 further comprising current turn-off means for turning off the current controlling device via the gate terminal when the current detection circuit detects load current in excess of a predetermined level.

Claim 10

The combination of any of claims 1 to 8 wherein said first branch includes first and third series-connected semiconductor devices; said second branch includes second and fourth series-connected semiconductor devices; said first and said fourth semiconductor devices operating in a transimpedance mode and each being controlled by bias signals; and said second and said third semiconductor devices being cross-connected with said first and said fourth semiconductor devices respectively to provide the respective said bias signals thereto.

Claim 11

The current sensing circuit of claim 9 wherein said first, second, third and fourth semiconductor devices comprise first, second, third and fourth transistors respectively, said first and said second transistors being one of two conductivity types and said third and said fourth transistors being the other of the two conductivity types.

Claim 12

The current sensing circuit of claim 10 wherein said first, second, third and fourth transistors are each bipolar transistors.

Claim 13

The current sensing circuit of claim 11 wherein the first main current terminal of the current controlling device is adapted to be connected to one polarity of a source of power having relatively opposite polarities, the second main current terminal of the current controlling device is adapted to be connected to one side of a load, the other side of the load being adapted to be connected to the other polarity of the source of power, and wherein both said first and said second transistors are PNP transistors and both said third and said fourth transistors are NPN transistors.

Claim 14

The current sensing circuit of claim 12 wherein said reference potential in the power delivery circuit, to which said first and second branches of said sensing circuit has said means for connection in common, is said other polarity of the source of power.

Claim 15

The current sensing circuit of any of claims 10 to 13 wherein the betas (β) of said first and said second transistors are substantially identical and the betas (β) of said third and said fourth transistors are substantially identical.

Claim 16

The current sensing circuit of any of claims 11 to 14 wherein said second and said third transistors are each connected in respective shorted base-to-collector configurations and wherein the base of said second transistor is connected to the base of said first transistor and the base of said third transistor is connected to the base of said fourth transistor.

Claim 17

The current sensing circuit of any of claims 1 to 15 wherein said impedance means in said first branch is a first resistor.

Claim 18

The current sensing circuit of any of claims 7 to 16 wherein said second branch circuit includes a respective second resistor in series circuit therewith.

Claim 19

The current sensing circuit of any of claims 1 to 15 wherein said impedance means in said first branch comprises a resistor, said resistor further being connected in series circuit in said second branch whereby said resistor is connected in common in said first and said second branches.

Claim 20

The current sensing circuit of any of claims 12 to 18 wherein said one polarity of a source of power is relatively more positive than said other polarity of the source of power such that said current switch is connected in the relatively more positive, or high, side of the power delivery circuit relative to the load.

Claim 21

The current sensing circuit of any of claims 12 to 19 further including fifth and sixth bipolar transistors, said fifth transistor being of the same conductivity type as said first and second transistors and said sixth transistor being of the same conductivity type as said third and fourth transistors, the emitter-base junction of said fifth transistor being connected between the base and collector of said second transistor, the emitter-base junction of said sixth transistor being connected between the base and collector of said third transistor, the collector of said fifth transistor being adapted to be connected to the reference potential and the collector of said sixth transistor being adapted to be connected to said first auxiliary terminal of said current controlling device, whereby to reduce sensitivity to the betas (β) of the first, second, third and fourth transistors.

Claim 22

The current sensing circuit of any of claims 12 to 19 further including fifth and sixth bipolar transistors, said second and said third transistors each connected in respective shorted base-to-collector configurations, the fifth transistor having its emitter and collector connected in serial circuit in the second branch between said second and said fourth transistors, the sixth transistor having its emitter and collector connected in serial circuit in the first branch between said first and said third transistors, the bases of said fifth and said sixth transistors being connected to the collectors of said sixth and said fifth transistors respectively, whereby voltage drops between the emitters and collectors of the respective said fifth and sixth transistors serve to limit the voltage drops between the emitters and collectors of the respective said first and fourth transistors to thereby reduce variations in the betas (β) of the first, second, third, and fourth transistors for variations in the voltage across the power delivery circuit.

Claim 23

A power delivery circuit of the H-bridge type including: a load leg having two end nodes and means to connect to a load; a power means for connection to a source of electrical power having a predetermined nominal voltage for supplying current to the load; a ground means for providing a path for returning load current to the source of electrical power; a first current path for supplying load current through the load in a first direction comprising a first high potential leg connected between the power means and a first end node of the load leg, and a first low potential leg connected between a second end node of the load leg and the ground means; and a second current path for supplying load current through the load in a second direction comprising a second high potential leg connected between the power means and the second end node of the load leg, and a second low potential leg connected between the first end node of the load leg and the ground means; the high and low potential legs each including a respective current switch, each said high potential leg current switch being multicellular with a plurality of terminals, including a first main current terminal connected to the power means, a second main current terminal connecting a majority of device cells to a respective end node of the load leg, a control terminal for controlling the switching state of the switch in response to a control signal, a first auxiliary terminal connected to one end of a minority of switch cells so as to provide a current generally proportional to the main switch current, and a second auxiliary terminal connected at one end to the majority of switch cells; the power delivery circuit further comprising first and second current detection circuits responsive to electrical conditions in the first and second high potential legs, respectively, for detection the current level in either of such legs; each current detection circuit comprising a first branch connected between the first auxiliary terminal and the ground means and including in serial circuit, a resistor providing a voltage at one end approximately proportional to the main switch current and a bias signal-controlled first bipolar transistor, and a second branch connected between the second auxiliary terminal and the ground means and including in serial circuit, a second bipolar transistor, the base of the second transistor being shorted to its collector and being connected to the base of the first transistor for providing a bias signal for the first transistor in the first branch whereby said voltage at said resistor one end is proportional to the actual main switch current within ±3% for variations in the source voltage in a range of at least ±25% of said nominal source voltage and variations between 100 and 500 in the gains (β) of said first and second transistors.

Claim 24

A power delivery circuit of the H-bridge type including: a load leg having two end nodes and means to connect to a load; a power means for connection to a source of electrical power having a predetermined nominal voltage for supplying current to the load; a ground means for providing a path for returning load current to the source of electrical power; a first current path for supplying load current through the load in a first direction comprising a first high potential leg connected between the power means and a first end node of the load leg, and a first low potential leg connected between a second end node of the load leg and the ground means; and a second current path for supplying load current through the load in a second direction comprising a second high potential leg connected between the power means and the second end node of the load leg, and a second low potential leg connected between the first end node of the load leg and the ground means; the high and low potential legs each including a respective current switch, each said high potential leg current switch being multicellular with a plurality of terminals, including a first main current terminal connected to the power means, a second main current terminal connecting a majority of device cells to a respective end node of the load leg, a control terminal for controlling the switching state of the switch in response to a control signal, a first auxiliary terminal connected to one end of a minority of switch cells so as to provide a current generally proportional to the main switch current, and a second auxiliary terminal connected at one end to the majority of switch cells; the power delivery circuit further comprising first and second current detection circuits responsive to electrical conditions in the first and second high potential legs, respectively, for detection the current level in either of such legs; each current detection circuit comprising a first branch connected between the first auxiliary terminal and the ground means and including in serial circuit, a resistor providing a voltage at one end approximately proportional to the main switch current and a bias signal-controlled first bipolar transistor, and a second branch connected between the second auxiliary terminal and the ground means and including in serial circuit, a second bipolar transistor, the base of the second transistor being shorted to its collector and being connected to the base of the first transistor for providing a bias signal for the first transistor in the first branch whereby said voltage at said resistor one end is proportional to the actual main switch current within ±3% for variations in the source voltage in a range of at least ±25% of said nominal source voltage and variations between 100 and 500 in the gains (β) of said first and second transistors.

Claim 25

In an H-bridge power delivery circuit for a load, the H-bridge circuit including two upper arms adapted to be connected to a positive supply potential and two lower arms adapted to be connected to a reference potential, a respective current sensing MOSFET in each upper arm of said H-bridge and a respective switch in each lower arm of said H-bridge, each said current sensing MOSFET comprising a multi-cellular device with a first main current terminal, a gate terminal for receiving a control signal, a second main current terminal connecting a majority of device cells, a first auxiliary terminal connected at one end to a minority of device cells so as to provide a current generally proportional to the main device current, and a second auxiliary terminal connected at one end to the majority of device cells, and an improved current sensing circuit connected to said first and said second auxiliary terminals of each of said current sensing MOSFETs and to said reference potential for providing an output signal voltage approximately proportional to the main device current, the current sensing circuit comprising first and second branches, the first branch including, in serial circuit, first and third bipolar transistors and a sense resistor, the first transistor being connected to the first auxiliary terminal of the respective current sensing MOSFET and one end of the resistor being connected to the reference potential and the other end being connected to the third transistor at a node, the second branch including, in serial circuit, second and fourth bipolar transistors, the second transistor being connected to the second auxiliary terminal of the respective current sensing MOSFET and the fourth transistor being connected to the sense resistor at said node, said first and said fourth transistors each being controlled by respective bias signals provided by cross-connection with said second and said third transistors respectively, and wherein said output signal voltage comprises the voltage appearing at said node.

Claim 26

In an H-bridge power delivery circuit for a load, the H-bridge circuit including two upper arms adapted to be connected to a positive supply potential and two lower arms adapted to be connected to a reference potential, a respective current sensing MOSFET in each upper arm of said H-bridge and a respective switch in each lower arm of said H-bridge, each said current sensing MOSFET comprising a multi-cellular device with a first main current terminal, a gate terminal for receiving a control signal, a second main current terminal connecting a majority of device cells, a first auxiliary terminal connected at one end to a minority of device cells so as to provide a current generally proportional to the main device current, and a second auxiliary terminal connected at one end to the majority of device cells, and an improved current sensing circuit connected to said first and said second auxiliary terminals of each of said current sensing MOSFETs and to said reference potential for providing an output signal voltage approximately proportional to the main device current, the current sensing circuit comprising first and second branches, the first branch including, in serial circuit, first and third bipolar transistors and a sense resistor, the first transistor being connected to the first auxiliary terminal of the respective current sensing MOSFET and one end of the resistor being connected to the reference potential and the other end being connected to the third transistor at a node, the second branch including, in serial circuit, second and fourth bipolar transistors, the second transistor being connected to the second auxiliary terminal of the respective current sensing MOSFET and the fourth transistor being connected to the sense resistor at said node, said first and said fourth transistors each being controlled by respective bias signals provided by cross-connection with said second and said third transistors respectively, and wherein said output signal voltage comprises the voltage appearing at said node.