Patent EP0395348A2 successfully refreshed from Google Patents.
EP0395348A2
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Method and apparatus for multi-gauge computation
Assignee: Apple Inc
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Filing: 1990-04-24
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Granted: —
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Expires: 2010-04-24
Abstract
Abstract Methods and apparatus are provided for performing multi-gauge arithmetic operations in a microprocessor CPU. Special purpose instructions facilitate parallel processing of individual bytes or half words of data words without requiring that the processor's mode be separately controlled. A byte/half word mode flag is provided to control the "width" of narrow gauge operation. Add partial, subtract partial and compare partial instructions operate on corresponding bytes or half words of two operands and return independent byte or half word results. Multiply partial instructions multiply byte or half word muitiplicands by a common multiplier and return independent byte or half word products. The multi-gauge arithmetic operations of the present invention have particular application to graphics processing where repetitive operations are performed on large arrays of pixel data.
Inventors
- 👤 Allen J. Baum
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 19:51
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015; G06F9/30036; G06F9/30038; G06F9/30094; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/30181; G06F9/30185; G06F9/30189; G06F9/30192
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
115 words
In a digital computer, a method for selectively performing a plurality of arithmetic operations in parallel comprising the steps of: (a) providing flag means for designating an integer value k; (b) providing arithmetic means for performing a selected arithmetic operation simultaneously on k independent sets of operands; (c) specifying a value of k from a plurality of permissible values; (d) asserting k independent first operands at said arithmetic means; (e) asserting at least one second operand at said arithmetic means; and (f) computing k independent results by performing said selected arithmetic operation on each of said first operands; whereby a selectively variable number k of parallel arithmetic operations are performed on k independent first operands.
Claim 2
Dependent Claim
115 words
In a digital computer, a method for selectively performing a plurality of arithmetic operations in parallel comprising the steps of: (a) providing flag means for designating an integer value k; (b) providing arithmetic means for performing a selected arithmetic operation simultaneously on k independent sets of operands; (c) specifying a value of k from a plurality of permissible values; (d) asserting k independent first operands at said arithmetic means; (e) asserting at least one second operand at said arithmetic means; and (f) computing k independent results by performing said selected arithmetic operation on each of said first operands; whereby a selectively variable number k of parallel arithmetic operations are performed on k independent first operands.
Claim 3
Dependent Claim
15 words
The method of claim 1 wherein said flag means is included in a status register.
Claim 4
Dependent Claim
15 words
The method of claim 1 wherein said flag means is included in an instruction code.
Claim 5
Dependent Claim
12 words
The method of claim 1 wherein said selected arithmetic operation is addition.
Claim 6
Dependent Claim
11 words
The method of claim 1 wherein said selected arithmetic operations subtraction.
Claim 7
Dependent Claim
12 words
The method of claim 1 wherein said selected arithmetic operation is comparison.
Claim 8
Dependent Claim
12 words
The method of claim 1 wherein said selected arithmetic operation is multiplication.
Claim 9
Dependent Claim
10 words
The method of claim 6 wherein said multiplication is signed.
Claim 10
Dependent Claim
10 words
The method of claim 7 wherein said multiplication is unsigned.
Claim 11
Dependent Claim
7 words
The method of claim 1 wherein k=2.
Claim 12
Dependent Claim
7 words
The method of claim 1 wherein k=4.
Claim 13
Dependent Claim
17 words
The method of claim 1 wherein each of said k independent results include a carry condition code.
Claim 14
Dependent Claim
16 words
The method of claim 1 wherein k independent second operands are asserted at said arithmetic means.
Claim 15
Dependent Claim
12 words
The method of claim 13 wherein said selected arithmetic operation is addition.
Claim 16
Dependent Claim
12 words
The method of claim 13 wherein said selected arithmetic operation is subtraction.
Claim 17
Dependent Claim
12 words
The method of claim 13 wherein said selected arithmetic operation is comparison.
Claim 18
Dependent Claim
27 words
The method of claim 1 further comprising the step of providing a first register means for storing a first M-bit word comprising k independent N-bit first operands.
Claim 19
Dependent Claim
12 words
The method of claim 17 wherein said selected arithmetic operation is addition.
Claim 20
Dependent Claim
12 words
The method of claim 17 wherein said selected arithmetic operation is subtraction.
Claim 21
Dependent Claim
12 words
The method of claim 17 wherein said selected arithmetic operation is comparison.
Claim 22
Dependent Claim
12 words
The method of claim 17 wherein said selected arithmetic operation is multiplication.
Claim 23
Dependent Claim
10 words
The method of claim 21 wherein said multiplication is signed.
Claim 24
Dependent Claim
10 words
The method of claim 21 wherein said multiplication is unsigned.
Claim 25
Dependent Claim
7 words
The method of claim 17 wherein M=32.
Claim 26
Dependent Claim
9 words
The method of claim 24 wherein k=2 and N=16.
Claim 27
Dependent Claim
9 words
The method of claim 24 wherein k=4 and N=8.
Claim 28
Dependent Claim
27 words
The method of claim 17 further comprising the step of providing a second register means for storing a second M-bit word comprising k independent N-bit second operands.
Claim 29
Dependent Claim
54 words
The method of claim 1 further comprising the step of setting a zero condition code to a logical value if any one of said k independent results is equal to zero and setting said zero condition code to an opposite logical value if all of said k independent results are not equal to zero.
Claim 30
Dependent Claim
138 words
In a digital computer, a method for selectively performing a plurality of arithmetic operations in parallel comprising the steps of: (a) providing a multiplying means for performing an M-bit multiplication and which is selectively partitionable into a plurality of independent sub-multiplying means, each such sub-multiplying means for performing an N-bit multiplication; (b) providing a first register means for storing a multiplier; (c) providing a second register means for storing an M-bit word representing a plurality of N-bit multiplicands; (d) asserting said plurality of N-bit multiplicands at said multiplying means; (e) asserting said multiplier at said multiplying means; (f) computing a plurality of independent products of said respective plurality of multiplicands and said multiplier; (g) truncating each of said plurality of independent products to an N-bit result; and (h) concatenating said plurality of N-bit results into an M-bit word.
Claim 31
Dependent Claim
138 words
In a digital computer, a method for selectively performing a plurality of arithmetic operations in parallel comprising the steps of: (a) providing a multiplying means for performing an M-bit multiplication and which is selectively partitionable into a plurality of independent sub-multiplying means, each such sub-multiplying means for performing an N-bit multiplication; (b) providing a first register means for storing a multiplier; (c) providing a second register means for storing an M-bit word representing a plurality of N-bit multiplicands; (d) asserting said plurality of N-bit multiplicands at said multiplying means; (e) asserting said multiplier at said multiplying means; (f) computing a plurality of independent products of said respective plurality of multiplicands and said multiplier; (g) truncating each of said plurality of independent products to an N-bit result; and (h) concatenating said plurality of N-bit results into an M-bit word.
Claim 32
Dependent Claim
7 words
The method of claim 29 wherein M=32.
Claim 33
Dependent Claim
7 words
The method of claim 30 wherein N=8.
Claim 34
Dependent Claim
7 words
The method of claim 30 wherein N=16.
Claim 35
Dependent Claim
28 words
The method of claim 29 further comprising the step of asserting a plurality of respective sign bits at said multiplying means for each of said plurality of multiplicands.
Claim 36
Dependent Claim
30 words
The method of claim 33 further comprising the step of providing a status register for storing said plurality of sign bits prior to the assertion thereof at said multiplying means.
Claim 37
Dependent Claim
40 words
The method of claim 33 further comprising the step, before the step of asserting said plurality of sign bits at said multiplying means, of determining each of said plurality of sign bits as a result of a respective arithmetic operation.
Claim 38
Dependent Claim
17 words
The method of claim 35 wherein said result is a carry condition of said respective arithmetic operation.
Claim 39
Dependent Claim
11 words
The method of claim 36 wherein said arithmetic operation is addition.
Claim 40
Dependent Claim
11 words
The method of claim 36 wherein said arithmetic operation is subtraction.
Claim 41
Dependent Claim
11 words
The method of claim 36 wherein said arithmetic operation is comparison.
Claim 42
Dependent Claim
89 words
In a digital computer for performing data processing functions on data words, said digital computer adapted to perform arithmetic operations in parallel on a plurality of subsets of said data words, a method for monitoring results of said arithmetic operations comprising the steps of: (a) providing a plurality of carry condition codes associated with said subsets of data words for indicating a carry condition in the respective subsets of a result of one of said arithmetic operations; (b) providing register means for storing said plurality of carry condition codes.
Claim 43
Dependent Claim
89 words
In a digital computer for performing data processing functions on data words, said digital computer adapted to perform arithmetic operations in parallel on a plurality of subsets of said data words, a method for monitoring results of said arithmetic operations comprising the steps of: (a) providing a plurality of carry condition codes associated with said subsets of data words for indicating a carry condition in the respective subsets of a result of one of said arithmetic operations; (b) providing register means for storing said plurality of carry condition codes.
Claim 44
Dependent Claim
34 words
The method of claim 40 further comprising the step of logically ORing said plurality of carry condition codes to determine if a carry condition occurred in any one of said subsets of said result.
Claim 45
Dependent Claim
27 words
The method of claim 40 further comprising the step of extending each of said plurality of carry condition codes into their respective subsets of a data word.
References Cited (Backward Citations)
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