Method of manufacturing a logic semiconductor device having non-volatile memory

Claim 1

A semiconductor device in which a non-volatile memory and a logic circuit portion are formed on a single semiconductor substrate, characterized by com­prising: a semiconductor substrate (101, 201); a memory cell portion formed on a first surface of said substrate (101, 201); a logic circuit portion formed on a second surface of said substrate (101, 201); a cell transistor consisting of said memory cell portion; and a transistor consisting of said logic circuit por tion, wherein a floating gate (107, 207) of said cell transistor of said memory cell and a gate (112b, 217b) of said transistor of said logic circuit portion are formed by conductive layers formed in different steps.

Claim 4

A method of manufacturing a semiconductor device in which a non-volatile memory and a logic circuit portion are formed on a single semiconductor substrate, characterized by comprising the steps of: forming a first insulating film (102) serving as an element isolating region on said semiconductor substrate (101); partially removing said first insulating film (102) to expose a memory cell portion forming region and a logic circuit portion forming region on said substrate (101); forming a second insulating film which is to serve as a first gate insulating film (103) of a cell transistor of said memory cell portion; doping an impurity for controlling a threshold value of said cell transistor in a channel region of said cell transistor of said memory cell portion; forming a first conductive layer on an entire surface of a resultant structure; patterning said first conductive layer to form a floating gate of said memory cell portion of said memory cell portion and to expose said logic circuit portion forming region; forming a third insulating film which is to serve as a gate insulating film (108b) of a transistor of said logic circuit portion and as a second gate insulating film of said cell transistor of said memory cell portion on an entire surface of a resultant structure; doping an impurity for controlling a threshold value of said transistor in a channel region of said transistor of said logic circuit portion; and patterning said second conductive layer to form a control gate (112a) of said cell transistor of said memory cell portion and a gate (112b) of said transistor of said logic circuit portion.

Claim 5

A method of manufacturing a semiconductor device in which a non-volatile memory and a logic circuit portion are formed on a single semiconductor substrate, characterized by comprising the steps of: forming a first insulating film (102) serving as an element isolating region on said semiconductor substrate (101); partially removing said first insulating film (102) to expose a memory cell portion forming region and a logic circuit portion forming region on said substrate (101); forming a second insulating film which is to serve as a first gate insulating film (103) of a cell transistor of said memory cell portion; doping an impurity for controlling a threshold value of said cell transistor in a channel region of said cell transistor of said memory cell portion; forming a first conductive layer on an entire surface of a resultant structure; patterning said first conductive layer to form a floating gate of said memory cell portion of said memory cell portion and to expose said logic circuit portion forming region; forming a third insulating film which is to serve as a gate insulating film (108b) of a transistor of said logic circuit portion and as a second gate insulating film of said cell transistor of said memory cell portion on an entire surface of a resultant structure; doping an impurity for controlling a threshold value of said transistor in a channel region of said transistor of said logic circuit portion; and patterning said second conductive layer to form a control gate (112a) of said cell transistor of said memory cell portion and a gate (112b) of said transistor of said logic circuit portion.

Claim 6

A method of manufacturing a semiconductor device in which a non-volatile memory and a logic circuit portion are formed on a single semiconductor substrate, characterized by comprising the steps of: forming a first insulating film (202) which is to serve as an element isolating region on a surface of a semiconductor substrate (201); partially removing said first insulating film (202) to form a memory cell portion forming region and a logic circuit portion forming region of said substrate (202); forming a second insulating film which is to serve as a first gate insulating film (203) of a cell tran­sistor of said memory cell portion on an entire surface of a resultant structure; doping an impurity for controlling a threshold value of said cell transistor in a channel region of said cell transistor of said memory cell portion; forming a first conductive layer on an entire surface; patterning said first conductive layer to form a floating gate (207) of said memory cell of said memory cell portion and to expose said logic circuit portion forming region; forming an insulating layer consisting of a plu­rality of insulating films on an entire surface of a resultant structure; patterning said insulating layer to expose said logic circuit portion forming region on the substrate (201); forming a second insulating film (212) which is to serve as a sacrificial oxide film of said logic circuit portion on an entire surface of a resultant structure; doping an impurity for controlling a threshold value of a transistor of said logic circuit portion in said logic circuit portion through said second insu­lating film (212); removing said second insulating film (212); forming a third insulating film (216) on an entire surface of a resultant structure; forming a second conductive layer (217) on an entire surface of a resultant structure; doping an impurity in said second conductive layer (217); and patterning said insulating layer remaining on said second conductive layer (217) and said memory cell portion to form a control gate (217a), a second gate insulating film, and a floating gate (207a) of said memory cell portion and a gate (217b) and a gate insu­lating film (216b) of said logic circuit portion.

Claim 7

A method of manufacturing a semiconductor device in which a non-volatile memory and a logic circuit portion are formed on a single semiconductor substrate, characterized by comprising the steps of: forming a first insulating film (202) which is to serve as an element isolating region on a surface of a semiconductor substrate (201); partially removing said first insulating film (202) to form a memory cell portion forming region and a logic circuit portion forming region of said substrate (202); forming a second insulating film which is to serve as a first gate insulating film (203) of a cell tran­sistor of said memory cell portion on an entire surface of a resultant structure; doping an impurity for controlling a threshold value of said cell transistor in a channel region of said cell transistor of said memory cell portion; forming a first conductive layer on an entire surface; patterning said first conductive layer to form a floating gate (207) of said memory cell of said memory cell portion and to expose said logic circuit portion forming region; forming an insulating layer consisting of a plu­rality of insulating films on an entire surface of a resultant structure; patterning said insulating layer to expose said logic circuit portion forming region on the substrate (201); forming a second insulating film (212) which is to serve as a sacrificial oxide film of said logic circuit portion on an entire surface of a resultant structure; doping an impurity for controlling a threshold value of a transistor of said logic circuit portion in said logic circuit portion through said second insu­lating film (212); removing said second insulating film (212); forming a third insulating film (216) on an entire surface of a resultant structure; forming a second conductive layer (217) on an entire surface of a resultant structure; doping an impurity in said second conductive layer (217); and patterning said insulating layer remaining on said second conductive layer (217) and said memory cell portion to form a control gate (217a), a second gate insulating film, and a floating gate (207a) of said memory cell portion and a gate (217b) and a gate insu­lating film (216b) of said logic circuit portion.