Patent EP0394575B1 successfully refreshed from Google Patents.
EP0394575B1
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EP
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Programmable logic device
Assignee: Xilinx Inc
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Filing: 1989-04-28
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Granted: 1995-08-16
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Expires: 2009-04-28
Abstract
No abstract record available.
Inventors
- 👤 Cecil H. Kaplinsky
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 10:22
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17764; H03K19/17704; H03K19/17736; H03K19/1778; H03K19/17792; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/52; H04Q3/521
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
268 words
A programmable logic device comprising, a matrix of functional units (20-28), each functional unit having a set of inputs (29) and a set of outputs (30), each functional unit being individually programmable for carrying out one or more specified logic functions, each functional unit (20-28) being a programmable logic device with an AND array (48) and an OR array (50) connected to the AND array, a first set (31) of conductive lines, each line (31a-31i) of said first set being permanently connected to an output from an OR array (50) of one of said functional units (20-28), a second set (32) of conductive lines, each line (32a-32l) of said second set being permanently connected directly to an input to an AND array (48) of one of said functional units (20-28), wherein said second set of conductive lines cross said first set of conductive lines, areas where said first and second sets of conductive lines cross forming programmable interconnection matrices (33), said matrices including programmable links (66) at the intersections of each conductive line (31a-31i) of the first set (31) with a conductive line (32a-32l) of the second set (32), each of said links (66) being selectively openable and closeable so as to connect any output (30) of any functional unit (20-28) to any input (29) of any functional unit (20-28), a plurality of input pins (34a, 34b), each input pin being connectable to at least one conductive line of said second set (32), and a plurality of output pins (40a, 40b), each output pin being selectively connected to at least one conductive line of said first set (31).
Claim 2
Dependent Claim
30 words
The device of claim 1 wherein said functional units (20-28) comprise programmable logic arrays, both said AND arrays (48) and said OR arrays (50) of said functional units being programmable.
Claim 3
Dependent Claim
25 words
The device of claim 1 wherein said programmable logic devices further include registers (64) programmably connected between said OR array and said set of outputs.
Claim 4
Dependent Claim
18 words
The device of claim 1 wherein said functional units (20-28) and said interconnection matrices (33) are mask programmable.
Claim 5
Dependent Claim
18 words
The device of claim 1 wherein said functional units (20-28) and said interconnection matrices (33) are fuse programmable.
Claim 6
Dependent Claim
19 words
The device of claim 1 wherein said functional units (20-28) and said interconnection matrices (33) are EPROM switch programmable.
Claim 7
Dependent Claim
19 words
The device of claim 1 wherein said functional units (20-28) and said interconnection matrices (33) are EEPROM switch programmable.
Claim 8
Dependent Claim
64 words
The device of claim 1 wherein said output pins are indirectly connected to selected conductive lines of said first set (31) via at least one output module (46a, 46b), each output module comprising a programmable logic device with inputs (42a, 42b) connected to said selected conductive lines and with outputs connected to said output pins (40a, 40b), said programmable logic device generating control signals.
Claim 9
Dependent Claim
22 words
The device of claim 8 whreein said programmable logic device forming said output module (46a, 46b) generates both data and control signals.
Claim 10
Dependent Claim
91 words
The device of claim 1 wherein each of said conductive lines in said first set (31) comprises, a main line (31a) permanently connected to an output (30) of one of said functional units (20-28), and a plurality of branching lines (31a′, 31a˝) connected to said main line (31a) by series switches (81a′, 81a˝), said branching lines (31a′, 31a˝) crossing said second set of conductive lines (32a-32l) within said programmable interconnection matrices (33), said branching lines (31a′, 31a˝) being selectively connectable to said second set of conductive lines through programmable links (66).
Claim 11
Dependent Claim
81 words
The device of claim 1 wherein each of said conductive lines in said second set (32) comprises, a main line (32a) permanently connected to an input (29) of one of said functional units (20-28), and a plurality of branching lines connected to said main line by series switches, said branching lines crossing said first set of conductive lines within said programmable interconnection matrices, said branching lines being selectively connectable to said first set (31) of conductive lines through programmable links (66).
Claim 12
Dependent Claim
102 words
The device of claim 2 wherein each said product lines (56) leading from said AND array (48) branch into a first product line (88) and a second product line (86), one of said first and second product lines (86, 88) being connected to said product line (56) leading from said AND array (48) by a programmable link (84), said first product line (88) being connectable (90) to any of a plurality of OR gate input lines (92) of said programmable OR array (50′), said second product line (86) being connectable (90) to only a subset of said OR gate input lines (92).
Claim 13
Dependent Claim
30 words
The device of claim 2 wherein said product lines (56; 179) connect (63; 189) to subsets of OR gate input lines (60; 183) of said programmable OR array (50˝; 180).
Claim 14
Dependent Claim
23 words
The device of claim 2 further comprising a specialized unit (182) with dedicated logic programmably connected (190) to said programmable OR array (180).
Claim 15
Dependent Claim
61 words
The device of claim 1 wherein a subset (34c) of said plurality of input pins (34a-34c) are directly connectable (117) to inputs (116) of a functional unit (122) that is programmable for carrying out a simple logic function, outputs (124) of said functional unit (122) being directly connectable (123) to a subset (126) of said plurality of output pins (40a-40b, 126).
Claim 16
Dependent Claim
16 words
The device of claim 1 wherein one of said functional units is a memory unit (130).
Claim 17
Dependent Claim
17 words
The device of claim 1 wherein one of said functional units is an arithmetic logic unit (132).
Claim 18
Dependent Claim
103 words
The device of claim 1 further comprising a first multiplexer (134) and a second multiplexer (136), said first multiplexer (134) being permanently connected to said first set of conductive lines (31), said second multiplexer (136) being permanently connected to said second set of conductive lines (32), each of said multiplexers (134, 136) being connectable via gates (138, 140) to at least a subset (34a, 40a) of said input (34a-34b) and output (40a-40b) pins, said multiplexers (134, 136) being connected to said conductive lines (31, 32) so as to provide access to said inputs (29) and outputs (30) of a selected functional unit (20-28).
Claim 19
Dependent Claim
52 words
The device of claim 1 further comprising means (145, 147, 149) communicating with said conductive lines (21) for monitoring logic states on a first subset of said conductive lines (31) and for transmitting selected logic state information to an output (150) in response to a programmed test condition of said monitored states.
Claim 20
Dependent Claim
106 words
The device of claim 19 wherein said monitoring and transmitting means comprises a programmable AND array (145) connected to said first set of conductive lines (31), a random access memory (147) connected to said programmable AND array (145) and a set of pins (149, 150) connected to said random access memory (147) for inputting programming information into and for reading logic state information out of said random access memory (147), said programmable AND array (145) and said random access memory (147) responsive to programmed condition on a first subset of said conductive lines (31, 36a-b) for storing logic state information in said random access memory (147).
Claim 21
Dependent Claim
148 words
The device of claim 1 wherein each conductive line (31) of said first set includes a main line (31a) permanently connected to an output (30) of one of said programmable logic devices (20-28) and a plurality of branching lines (31a′, 31a˝) connected to said main line (31a) by series switches (81a′, 81a˝) and each conductive line (32) of said second set includes a main line (32a) pemanently connected to an input (29) of one of said programmable logic devices (20-28) and a plurality of branching lines connected to said main line (32a) by series switches, said branching lines of said first and second sets of conductive lines (31, 32) crossing at areas forming said programmable interconnection matrices (33), programmable links (66) of said matrices (33) being disposed at the intersections of each branching line of the first set (31) with a branching line of the second set (32).
Claim 22
Dependent Claim
144 words
The device of claim 1 wherein said functional units (20-28, 20a-28a), first and second sets of conductive lines (31, 32), programmable interconnection matrices (33), input pins (34a-34d) and output pins (40a-40d) are organized as a pair of distinct first and second subunits (160, 162), said device further comprising a switching matrix (164) disposed between said first and second subunits (160, 162), said switching matrix (164) having central connect lines (166) programmably connected to said at least one input line (36a-36d) and said first set of conductive lines (31) of each said subunit (160, 162), said switching matrix also having two sets of lead lines (168, 169) connectable to said central connect lines (166), each set of lead lines (168, 169) being programmably connectable to at least one output line (42a-42d) and said second set of conductive lines (32) of one said subunit (160, 162).
References Cited (Backward Citations)
No citation records indexed.
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