Patent US1980849A successfully refreshed from Google Patents.
Patent EP0393487A2 successfully refreshed from Google Patents.
EP0393487A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Display device driving circuit
Assignee: Sharp Corp
•
Filing: 1990-04-11
•
Granted: —
•
Expires: 2010-04-11
Abstract
Abstract A display device driving circuit for converting a binary display data into an AC signal having no DC component and supplying the AC signal to a display device including, a synchronizing circuit (26,27) for receiving the display data, a binary modulating signal and a clock signal and for synchronizing the display data and the modulating signal with the clock signal, a decoder (25) connected to the synchronizing circuit (26,27) for generating a signal having a logic level corresponding to logic levels of the synchronized display data and modulating signal, and a power supply circuit (18) connected to the decoder (25) for outputting a voltage having an amplitude corresponding to the logic level of the signal received from the decoder to the display device (12).
Inventors
- 👤 Taiji Iizuka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 19:05
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3685
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
122 words
A display device driving circuit for converting a binary display data into an AC signal having no DC component and supplying said AC signal to a display device (12) comprising: synchronizing means (26,27) for receiving said display data, a binary modulating signal and a clock signal and for synchronizing said display data and said modulating signal with said clock signal; decoder means (25) connected to said synchronizing means for generating a signal having a logic level corresponding to logic levels of said synchronized display data and modulating signal; and power supply means (18) connected to said decoder means for outputting a voltage having an amplitude corresponding to said logic level of said signal received from said decoder means to said display device.
Claim 2
Dependent Claim
122 words
A display device driving circuit for converting a binary display data into an AC signal having no DC component and supplying said AC signal to a display device (12) comprising: synchronizing means (26,27) for receiving said display data, a binary modulating signal and a clock signal and for synchronizing said display data and said modulating signal with said clock signal; decoder means (25) connected to said synchronizing means for generating a signal having a logic level corresponding to logic levels of said synchronized display data and modulating signal; and power supply means (18) connected to said decoder means for outputting a voltage having an amplitude corresponding to said logic level of said signal received from said decoder means to said display device.
Claim 3
Dependent Claim
58 words
A circuit according to claim 1, wherein said synchronizing means comprise a first D-type flip-flop (26) which receives said display data at one input thereof and said clock signal at the other input thereof, and a second D-type flip-flop (27) which receives said modulating signal at one input thereof and said clock signal at the other input thereof.
Claim 4
Dependent Claim
136 words
A circuit according to claim 2, wherein said decoder means comprise a first and a second NAND gates and a first and a second AND gates, one output of said first D-type flip-flop being connected to one input of said first NAND gate and to one input of said second AND gate, the other output of said first D-type flip-flop being connected to one input of said second NAND gate and to one input of said first AND gate, one output of said second D-type flip-flop being connected to the other input of said first AND gate and to the other input of said second AND gate, the other output of said second D-type flip-flop being connected to the other input of said first NAND gate and to the other input of said second NAND gate.
Claim 5
Dependent Claim
157 words
A circuit according to claim 3, wherein said power supply means comprise first and second FETs of P-channel type, and third and fourth FETs of N-channel type, an output of said first NAND gate being connected to a gate of the first FET, an output of said second NAND gate being connected to a gate of the second FET, an output of said first AND gate being connected to a gate of the third FET, an output of said second AND gate being connected to a gate of the fourth FET, a voltage of first level being applied to a source of the first FET, a voltage of second level being applied to a source of the second FET, a voltage of third level being applied to a source of the third FET, a voltage of fourth level being applied to a source of the fourth FET, drains of these FETs being connected to a common node.
Claim 6
Dependent Claim
18 words
A circuit according to claim 1, wherein said display device is a matrix type liquid crystal display device.
Claim 7
Dependent Claim
28 words
A circuit according to claim 5, wherein an output of said power supply means is connected to a segment electrode of said matrix type liquid crystal display device.
Claim 8
Dependent Claim
28 words
A circuit according to claim 5, wherein an output of said power supply means is connected to a common electrode of said matrix type liquid crystal display device.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.